Skip to content

H
Hdlmake
Commit 969a2617 authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
Browse files
Options

Refactoring and renaming merge and tree actions

parent 3fd3c0a9
Hide whitespace changes
Inline Side-by-side
Showing with 24 additions and 36 deletions
hdlmake/action/__init__.py
View file @ 969a2617
...@@ -23,8 +23,8 @@ ...@@ -23,8 +23,8 @@
from .check_condition import CheckCondition from .check_condition import CheckCondition
from .check_manifest import CheckManifest from .check_manifest import CheckManifest
from .core import ActionCore from .core import ActionCore
from .merge_cores import MergeCores from .merge import ActionMerge
from .tree import Tree from .tree import ActionTree
from .synthesis import ActionSynthesis from .synthesis import ActionSynthesis
from .simulation import GenerateSimulationMakefile from .simulation import GenerateSimulationMakefile
......
hdlmake/action/merge_cores.py → hdlmake/action/merge.py
View file @ 969a2617
...@@ -32,33 +32,30 @@ from hdlmake.vlog_parser import VerilogPreprocessor ...@@ -32,33 +32,30 @@ from hdlmake.vlog_parser import VerilogPreprocessor
from .action import Action from .action import Action
class MergeCores(Action): class ActionMerge(Action):
def _check_merge_cores(self):
self._check_manifest_variable_is_equal_to("action", "synthesis")
if not self.env.options.dest:
logging.error("--dest must be given for merge-cores")
sys.exit("Exiting")
def merge_cores(self): def merge_cores(self):
self._check_all_fetched_or_quit() self._check_all_fetched_or_quit()
self._check_merge_cores()
logging.info("Merging all cores into one source file per language.") logging.info("Merging all cores into one source file per language.")
flist = self.build_file_set() flist = self.build_file_set()
base = self.env.options.dest base = self.env.options.dest
f_out = open(base+".vhd", "w") file_header = (
f_out.write("\n\n\n\n") "\n\n\n\n"
f_out.write("------------------------------ WARNING -------------------------------\n") "------------------------------ WARNING -------------------------------\n"
f_out.write("-- This code has been generated by hdlmake --merge-cores option --\n") "-- This code has been generated by hdlmake --merge-cores option --\n"
f_out.write("-- It is provided for your convenience, to spare you from adding --\n") "-- It is provided for your convenience, to spare you from adding --\n"
f_out.write("-- lots of individual source files to ISE/Modelsim/Quartus projects --\n") "-- lots of individual source files to ISE/Modelsim/Quartus projects --\n"
f_out.write("-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n") "-- mainly for Windows users. Please DO NOT MODIFY this file. If you --\n"
f_out.write("-- need to change something inside, edit the original source file --\n") "-- need to change something inside, edit the original source file --\n"
f_out.write("-- and re-genrate the merged version! --\n") "-- and re-genrate the merged version! --\n"
f_out.write("----------------------------------------------------------------------\n") "----------------------------------------------------------------------\n"
f_out.write("\n\n\n\n") "\n\n\n\n"
)
# Generate a VHDL file containing all the required VHDL files
f_out = open(base+".vhd", "w")
f_out.write(file_header)
for vhdl in flist.filter(VHDLFile): for vhdl in flist.filter(VHDLFile):
f_out.write("\n\n--- File: %s ----\n" % vhdl.rel_path()) f_out.write("\n\n--- File: %s ----\n" % vhdl.rel_path())
f_out.write("--- Source: %s\n" % vhdl.module.url) f_out.write("--- Source: %s\n" % vhdl.module.url)
...@@ -69,19 +66,9 @@ class MergeCores(Action): ...@@ -69,19 +66,9 @@ class MergeCores(Action):
#print("VHDL: %s" % vhdl.rel_path()) #print("VHDL: %s" % vhdl.rel_path())
f_out.close() f_out.close()
# Generate a VHDL file containing all the required VHDL files
f_out = open(base+".v", "w") f_out = open(base+".v", "w")
f_out.write(file_header)
f_out.write("\n\n\n\n")
f_out.write("////////////////////////////// WARNING ///////////////////////////////\n")
f_out.write("// This code has been generated by hdlmake --merge-cores option //\n")
f_out.write("// It is provided for your convenience, to spare you from adding //\n")
f_out.write("// lots of individual source files to ISE/Modelsim/Quartus projects //\n")
f_out.write("// mainly for Windows users. Please DO NOT MODIFY this file. If you //\n")
f_out.write("// need to change something inside, edit the original source file //\n")
f_out.write("// and re-genrate the merged version! //\n")
f_out.write("//////////////////////////////////////////////////////////////////////\n")
f_out.write("\n\n\n\n")
for vlog in flist.filter(VerilogFile): for vlog in flist.filter(VerilogFile):
f_out.write("\n\n// File: %s\n" % vlog.rel_path()) f_out.write("\n\n// File: %s\n" % vlog.rel_path())
f_out.write("// Source: %s\n" % vlog.module.url) f_out.write("// Source: %s\n" % vlog.module.url)
...@@ -95,6 +82,7 @@ class MergeCores(Action): ...@@ -95,6 +82,7 @@ class MergeCores(Action):
f_out.write(vpp.preprocess(vlog.rel_path())) f_out.write(vpp.preprocess(vlog.rel_path()))
f_out.close() f_out.close()
# Handling NGC files
current_path = os.getcwd() current_path = os.getcwd()
for ngc in flist.filter(NGCFile): for ngc in flist.filter(NGCFile):
import shutil import shutil
......
hdlmake/action/tree.py
View file @ 969a2617
...@@ -24,7 +24,7 @@ from hdlmake.util import path ...@@ -24,7 +24,7 @@ from hdlmake.util import path
import logging import logging
class Tree(Action): class ActionTree(Action):
def generate_tree(self): def generate_tree(self):
try: try:
import networkx as nx import networkx as nx
......
hdlmake/module_pool.py
View file @ 969a2617
...@@ -35,13 +35,13 @@ from .util import path as path_mod ...@@ -35,13 +35,13 @@ from .util import path as path_mod
from . import fetch from . import fetch
from .env import Env from .env import Env
from .action import (CheckManifest, CheckCondition, ActionCore, from .action import (CheckManifest, CheckCondition, ActionCore,
MergeCores, Tree, GenerateSimulationMakefile, ActionMerge, ActionTree, GenerateSimulationMakefile,
ActionSynthesis, ActionSynthesis,
QsysHwTclUpdate) QsysHwTclUpdate)
class ModulePool(list, CheckManifest, CheckCondition, ActionCore, class ModulePool(list, CheckManifest, CheckCondition, ActionCore,
MergeCores, Tree, GenerateSimulationMakefile, ActionMerge, ActionTree, GenerateSimulationMakefile,
ActionSynthesis, ActionSynthesis,
QsysHwTclUpdate): QsysHwTclUpdate):
""" """
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment