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Commit c2eaa704 authored by Tristan Gingold's avatar Tristan Gingold
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test: improve coverage of isim.py

parent 8c3ea49e
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Showing with 11 additions and 3 deletions
testsuite/008ghdl/Makefile.ref
View file @ c2eaa704
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
# http://ohwr.org/projects/hdl-make/ # # http://ohwr.org/projects/hdl-make/ #
######################################## ########################################
TOP_MODULE := gate TOP_MODULE := gate3
PWD := $(shell pwd) PWD := $(shell pwd)
GHDL := ghdl GHDL := ghdl
...@@ -15,8 +15,10 @@ local: sim_pre_cmd simulation sim_post_cmd ...@@ -15,8 +15,10 @@ local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC := VERILOG_SRC :=
VERILOG_OBJ := VERILOG_OBJ :=
VHDL_SRC := ../files/gate.vhdl \ VHDL_SRC := ../files/gate.vhdl \
../files/gate3.vhd \
VHDL_OBJ := work/gate/.gate_vhdl \ VHDL_OBJ := work/gate/.gate_vhdl \
work/gate3/.gate3_vhd \
simulation: $(VERILOG_OBJ) $(VHDL_OBJ) simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
$(GHDL) -e $(GHDL_OPT) $(TOP_MODULE) $(GHDL) -e $(GHDL_OPT) $(TOP_MODULE)
...@@ -27,6 +29,12 @@ work/gate/.gate_vhdl: ../files/gate.vhdl ...@@ -27,6 +29,12 @@ work/gate/.gate_vhdl: ../files/gate.vhdl
@mkdir -p $(dir $@) && touch $@ @mkdir -p $(dir $@) && touch $@
work/gate3/.gate3_vhd: ../files/gate3.vhd \
work/gate/.gate_vhdl
$(GHDL) -a $(GHDL_OPT) $<
@mkdir -p $(dir $@) && touch $@
# USER SIM COMMANDS # USER SIM COMMANDS
sim_pre_cmd: sim_pre_cmd:
......
testsuite/008ghdl/Manifest.py
View file @ c2eaa704
...@@ -2,6 +2,6 @@ action = "simulation" ...@@ -2,6 +2,6 @@ action = "simulation"
sim_tool="ghdl" sim_tool="ghdl"
top_module = "gate" top_module = "gate3"
files = [ "../files/gate.vhdl" ] files = [ "../files/gate3.vhd", "../files/gate.vhdl" ]
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