Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Commits
c6b03c2a
Commit
c6b03c2a
authored
May 24, 2017
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Refactor ModuleArgs and move back shell to util
parent
4ca4b16a
Hide whitespace changes
Inline
Side-by-side
Showing
13 changed files
with
34 additions
and
34 deletions
+34
-34
action.py
hdlmake/action/action.py
+1
-1
fetcher.py
hdlmake/fetch/fetcher.py
+1
-1
git.py
hdlmake/fetch/git.py
+1
-1
content.py
hdlmake/module/content.py
+22
-0
module.py
hdlmake/module/module.py
+2
-24
ise.py
hdlmake/tools/ise.py
+1
-1
isim.py
hdlmake/tools/isim.py
+1
-1
make_sim.py
hdlmake/tools/make_sim.py
+1
-1
make_syn.py
hdlmake/tools/make_syn.py
+1
-1
makefile.py
hdlmake/tools/makefile.py
+1
-1
quartus.py
hdlmake/tools/quartus.py
+1
-1
sim_makefile_support.py
hdlmake/tools/sim_makefile_support.py
+1
-1
shell.py
hdlmake/util/shell.py
+0
-0
No files found.
hdlmake/action/action.py
View file @
c6b03c2a
...
...
@@ -29,7 +29,7 @@ import logging
import
sys
from
hdlmake.tools
import
load_syn_tool
,
load_sim_tool
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.util.termcolor
import
colored
from
hdlmake
import
new_dep_solver
as
dep_solver
from
hdlmake
import
fetch
as
fetch_mod
...
...
hdlmake/fetch/fetcher.py
View file @
c6b03c2a
...
...
@@ -23,7 +23,7 @@
from
__future__
import
absolute_import
import
os
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
class
Fetcher
(
object
):
...
...
hdlmake/fetch/git.py
View file @
c6b03c2a
...
...
@@ -24,7 +24,7 @@
from
__future__
import
absolute_import
import
os
from
hdlmake.util
import
path
as
path_utils
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
import
logging
from
.constants
import
GIT
from
.fetcher
import
Fetcher
...
...
hdlmake/module/content.py
View file @
c6b03c2a
...
...
@@ -9,6 +9,28 @@ from .core import ModuleCore
import
six
class
ModuleArgs
(
object
):
"""This class is just a container for the main Module args"""
def
__init__
(
self
):
self
.
parent
=
None
self
.
url
=
None
self
.
source
=
None
self
.
fetchto
=
None
def
set_args
(
self
,
parent
,
url
,
source
,
fetchto
):
"""Set the module arguments"""
self
.
parent
=
parent
self
.
url
=
url
self
.
source
=
source
self
.
fetchto
=
fetchto
def
get_args
(
self
):
"""Get the module arguments"""
return
self
.
parent
,
self
.
url
,
self
.
source
,
self
.
fetchto
class
ModuleContent
(
ModuleCore
):
"""Class providing the HDLMake module content"""
...
...
hdlmake/module/module.py
View file @
c6b03c2a
...
...
@@ -33,34 +33,12 @@ import os
import
logging
from
hdlmake.util
import
path
as
path_mod
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.manifest_parser
import
ManifestParser
from
.content
import
ModuleContent
from
.content
import
ModuleContent
,
ModuleArgs
import
six
class
ModuleArgs
(
object
):
"""This class is just a container for the main Module args"""
def
__init__
(
self
):
self
.
parent
=
None
self
.
url
=
None
self
.
source
=
None
self
.
fetchto
=
None
def
set_args
(
self
,
parent
,
url
,
source
,
fetchto
):
"""Set the module arguments"""
self
.
parent
=
parent
self
.
url
=
url
self
.
source
=
source
self
.
fetchto
=
fetchto
def
get_args
(
self
):
"""Get the module arguments"""
return
self
.
parent
,
self
.
url
,
self
.
source
,
self
.
fetchto
class
Module
(
ModuleContent
):
"""
...
...
hdlmake/tools/ise.py
View file @
c6b03c2a
...
...
@@ -29,7 +29,7 @@ import logging
from
.make_syn
import
ToolSyn
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
UCFFile
,
CDCFile
,
NGCFile
)
...
...
hdlmake/tools/isim.py
View file @
c6b03c2a
...
...
@@ -31,7 +31,7 @@ import os.path
import
logging
from
.make_sim
import
ToolSim
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
...
...
hdlmake/tools/make_sim.py
View file @
c6b03c2a
...
...
@@ -7,7 +7,7 @@ import string
import
logging
from
.makefile
import
ToolMakefile
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
...
...
hdlmake/tools/make_syn.py
View file @
c6b03c2a
...
...
@@ -6,7 +6,7 @@ import logging
import
string
from
.makefile
import
ToolMakefile
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
def
_check_synthesis_manifest
(
manifest_dict
):
...
...
hdlmake/tools/makefile.py
View file @
c6b03c2a
...
...
@@ -28,7 +28,7 @@ import os
import
logging
import
six
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
class
ToolMakefile
(
object
):
...
...
hdlmake/tools/quartus.py
View file @
c6b03c2a
...
...
@@ -30,7 +30,7 @@ import logging
from
.make_syn
import
ToolSyn
from
hdlmake.util
import
path
as
path_mod
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.srcfile
import
(
VHDLFile
,
VerilogFile
,
SVFile
,
DPFFile
,
SignalTapFile
,
SDCFile
,
QIPFile
,
QSYSFile
,
QSFFile
,
BSFFile
,
BDFFile
,
TDFFile
,
GDFFile
)
...
...
hdlmake/tools/sim_makefile_support.py
View file @
c6b03c2a
...
...
@@ -28,7 +28,7 @@ import os
import
string
from
.make_sim
import
ToolSim
from
hdlmake
import
shell
from
hdlmake
.util
import
shell
from
hdlmake.srcfile
import
VerilogFile
,
VHDLFile
,
SVFile
import
six
...
...
hdlmake/shell.py
→
hdlmake/
util/
shell.py
View file @
c6b03c2a
File moved
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment