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Hdlmake
Commit c6b03c2a authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Refactor ModuleArgs and move back shell to util

parent 4ca4b16a
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Showing with 34 additions and 34 deletions
hdlmake/action/action.py
View file @ c6b03c2a
...@@ -29,7 +29,7 @@ import logging ...@@ -29,7 +29,7 @@ import logging
import sys import sys
from hdlmake.tools import load_syn_tool, load_sim_tool from hdlmake.tools import load_syn_tool, load_sim_tool
from hdlmake import shell from hdlmake.util import shell
from hdlmake.util.termcolor import colored from hdlmake.util.termcolor import colored
from hdlmake import new_dep_solver as dep_solver from hdlmake import new_dep_solver as dep_solver
from hdlmake import fetch as fetch_mod from hdlmake import fetch as fetch_mod
......
hdlmake/fetch/fetcher.py
View file @ c6b03c2a
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
from __future__ import absolute_import from __future__ import absolute_import
import os import os
from hdlmake import shell from hdlmake.util import shell
class Fetcher(object): class Fetcher(object):
......
hdlmake/fetch/git.py
View file @ c6b03c2a
...@@ -24,7 +24,7 @@ ...@@ -24,7 +24,7 @@
from __future__ import absolute_import from __future__ import absolute_import
import os import os
from hdlmake.util import path as path_utils from hdlmake.util import path as path_utils
from hdlmake import shell from hdlmake.util import shell
import logging import logging
from .constants import GIT from .constants import GIT
from .fetcher import Fetcher from .fetcher import Fetcher
......
hdlmake/module/content.py
View file @ c6b03c2a
...@@ -9,6 +9,28 @@ from .core import ModuleCore ...@@ -9,6 +9,28 @@ from .core import ModuleCore
import six import six
class ModuleArgs(object):
"""This class is just a container for the main Module args"""
def __init__(self):
self.parent = None
self.url = None
self.source = None
self.fetchto = None
def set_args(self, parent, url, source, fetchto):
"""Set the module arguments"""
self.parent = parent
self.url = url
self.source = source
self.fetchto = fetchto
def get_args(self):
"""Get the module arguments"""
return self.parent, self.url, self.source, self.fetchto
class ModuleContent(ModuleCore): class ModuleContent(ModuleCore):
"""Class providing the HDLMake module content""" """Class providing the HDLMake module content"""
......
hdlmake/module/module.py
View file @ c6b03c2a
...@@ -33,34 +33,12 @@ import os ...@@ -33,34 +33,12 @@ import os
import logging import logging
from hdlmake.util import path as path_mod from hdlmake.util import path as path_mod
from hdlmake import shell from hdlmake.util import shell
from hdlmake.manifest_parser import ManifestParser from hdlmake.manifest_parser import ManifestParser
from .content import ModuleContent from .content import ModuleContent, ModuleArgs
import six import six
class ModuleArgs(object):
"""This class is just a container for the main Module args"""
def __init__(self):
self.parent = None
self.url = None
self.source = None
self.fetchto = None
def set_args(self, parent, url, source, fetchto):
"""Set the module arguments"""
self.parent = parent
self.url = url
self.source = source
self.fetchto = fetchto
def get_args(self):
"""Get the module arguments"""
return self.parent, self.url, self.source, self.fetchto
class Module(ModuleContent): class Module(ModuleContent):
""" """
......
hdlmake/tools/ise.py
View file @ c6b03c2a
...@@ -29,7 +29,7 @@ import logging ...@@ -29,7 +29,7 @@ import logging
from .make_syn import ToolSyn from .make_syn import ToolSyn
from hdlmake import shell from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile,
UCFFile, CDCFile, NGCFile) UCFFile, CDCFile, NGCFile)
......
hdlmake/tools/isim.py
View file @ c6b03c2a
...@@ -31,7 +31,7 @@ import os.path ...@@ -31,7 +31,7 @@ import os.path
import logging import logging
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile from hdlmake.srcfile import VerilogFile, VHDLFile
......
hdlmake/tools/make_sim.py
View file @ c6b03c2a
...@@ -7,7 +7,7 @@ import string ...@@ -7,7 +7,7 @@ import string
import logging import logging
from .makefile import ToolMakefile from .makefile import ToolMakefile
from hdlmake import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
......
hdlmake/tools/make_syn.py
View file @ c6b03c2a
...@@ -6,7 +6,7 @@ import logging ...@@ -6,7 +6,7 @@ import logging
import string import string
from .makefile import ToolMakefile from .makefile import ToolMakefile
from hdlmake import shell from hdlmake.util import shell
def _check_synthesis_manifest(manifest_dict): def _check_synthesis_manifest(manifest_dict):
......
hdlmake/tools/makefile.py
View file @ c6b03c2a
...@@ -28,7 +28,7 @@ import os ...@@ -28,7 +28,7 @@ import os
import logging import logging
import six import six
from hdlmake import shell from hdlmake.util import shell
class ToolMakefile(object): class ToolMakefile(object):
......
hdlmake/tools/quartus.py
View file @ c6b03c2a
...@@ -30,7 +30,7 @@ import logging ...@@ -30,7 +30,7 @@ import logging
from .make_syn import ToolSyn from .make_syn import ToolSyn
from hdlmake.util import path as path_mod from hdlmake.util import path as path_mod
from hdlmake import shell from hdlmake.util import shell
from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile, from hdlmake.srcfile import (VHDLFile, VerilogFile, SVFile, DPFFile,
SignalTapFile, SDCFile, QIPFile, QSYSFile, SignalTapFile, SDCFile, QIPFile, QSYSFile,
QSFFile, BSFFile, BDFFile, TDFFile, GDFFile) QSFFile, BSFFile, BDFFile, TDFFile, GDFFile)
......
hdlmake/tools/sim_makefile_support.py
View file @ c6b03c2a
...@@ -28,7 +28,7 @@ import os ...@@ -28,7 +28,7 @@ import os
import string import string
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake import shell from hdlmake.util import shell
from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile from hdlmake.srcfile import VerilogFile, VHDLFile, SVFile
import six import six
......
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