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Hdlmake
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d983c430
Commit
d983c430
authored
Mar 13, 2017
by
Javier D. Garcia-Lasheras
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Add a new Verilog test for Vivado simulation
parent
583bd9e0
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2 changed files
with
10 additions
and
1 deletion
+10
-1
vivado.py
hdlmake/tools/vivado.py
+1
-1
Manifest.py
tests/counter/sim/vivado/verilog/Manifest.py
+9
-0
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hdlmake/tools/vivado.py
View file @
d983c430
...
@@ -64,7 +64,7 @@ class ToolVivado(ToolXilinx, ToolSim):
...
@@ -64,7 +64,7 @@ class ToolVivado(ToolXilinx, ToolSim):
"$(PROJECT).cache"
,
"$(PROJECT).data"
,
"work"
,
"$(PROJECT).cache"
,
"$(PROJECT).data"
,
"work"
,
"$(PROJECT).runs"
,
"$(PROJECT).hw"
,
"xsim.dir"
,
"$(PROJECT).runs"
,
"$(PROJECT).hw"
,
"xsim.dir"
,
"$(PROJECT).ip_user_files"
,
"$(PROJECT_FILE)"
],
"$(PROJECT).ip_user_files"
,
"$(PROJECT_FILE)"
],
'mrproper'
:
[
"*.wdb"
]}
'mrproper'
:
[
"*.wdb"
,
"*.vcd"
]}
TCL_CONTROLS
=
{
'bitstream'
:
'$(TCL_OPEN)
\n
'
TCL_CONTROLS
=
{
'bitstream'
:
'$(TCL_OPEN)
\n
'
'launch_runs impl_1 -to_step write_bitstream'
'launch_runs impl_1 -to_step write_bitstream'
...
...
tests/counter/sim/vivado/verilog/Manifest.py
0 → 100644
View file @
d983c430
action
=
"simulation"
sim_tool
=
"vivado"
sim_top
=
"counter_tb"
sim_post_cmd
=
"xsim
%
s -gui"
%
sim_top
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
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