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Commit e21f2439 authored by Tristan Gingold's avatar Tristan Gingold
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Merge branch 'develop-vivado-worklib' into 'develop' 

Vivado: Compile to --work <library>

See merge request !26
parents b73be282 00bba9b7
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hdlmake/tools/vivado_sim.py
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...@@ -50,7 +50,7 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim): ...@@ -50,7 +50,7 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
'mrproper': ["*.wdb", "*.vcd"]} 'mrproper': ["*.wdb", "*.vcd"]}
SIMULATOR_CONTROLS = {'vlog': 'xvlog $<', SIMULATOR_CONTROLS = {'vlog': 'xvlog $<',
'vhdl': 'xvhdl $<', 'vhdl': 'xvhdl --work {work} $<',
'compiler': 'xelab -debug all $(TOP_MODULE) ' 'compiler': 'xelab -debug all $(TOP_MODULE) '
'-s $(TOP_MODULE)'} '-s $(TOP_MODULE)'}
...@@ -71,6 +71,8 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim): ...@@ -71,6 +71,8 @@ class ToolVivadoSim(ToolXilinxProject, MakefileSim):
def _makefile_sim_compilation(self): def _makefile_sim_compilation(self):
"""Generate compile simulation Makefile target for Vivado Simulator""" """Generate compile simulation Makefile target for Vivado Simulator"""
libs = self.get_all_libs()
self._makefile_sim_libs_variables(libs)
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)") self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler']) self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln() self.writeln()
......
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