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Hdlmake
Commits
ec10c20b
Commit
ec10c20b
authored
Nov 17, 2016
by
Javier D. Garcia-Lasheras
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Add VHDL and Verilog template files support to Vivado
parent
92c32a9f
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2 changed files
with
14 additions
and
2 deletions
+14
-2
srcfile.py
hdlmake/srcfile.py
+12
-0
vivado.py
hdlmake/tools/vivado.py
+2
-2
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hdlmake/srcfile.py
View file @
ec10c20b
...
...
@@ -182,6 +182,16 @@ class RAMFile(File):
pass
class
VHOFile
(
File
):
"""Xilinx VHDL Template File"""
pass
class
VEOFile
(
File
):
"""Xilinx Verilog Template File"""
pass
class
XCIFile
(
File
):
"""Xilinx Core IP File"""
pass
...
...
@@ -202,6 +212,8 @@ XILINX_FILE_DICT = {
'coe'
:
COEFile
,
'mif'
:
MIFFile
,
'ram'
:
RAMFile
,
'vho'
:
VHOFile
,
'veo'
:
VEOFile
,
'xci'
:
XCIFile
}
...
...
hdlmake/tools/vivado.py
View file @
ec10c20b
...
...
@@ -29,7 +29,7 @@ from .xilinx import ToolXilinx
from
.make_sim
import
ToolSim
from
hdlmake.srcfile
import
(
XDCFile
,
XCIFile
,
NGCFile
,
XMPFile
,
XCOFile
,
COEFile
,
BDFile
,
TCLFile
,
MIFFile
,
RAMFile
)
MIFFile
,
RAMFile
,
VHOFile
,
VEOFile
)
class
ToolVivado
(
ToolXilinx
,
ToolSim
):
...
...
@@ -48,7 +48,7 @@ class ToolVivado(ToolXilinx, ToolSim):
SUPPORTED_FILES
=
[
XDCFile
,
XCIFile
,
NGCFile
,
XMPFile
,
XCOFile
,
COEFile
,
BDFile
,
TCLFile
,
MIFFile
,
RAMFile
]
MIFFile
,
RAMFile
,
VHOFile
,
VEOFile
]
CLEAN_TARGETS
=
{
'clean'
:
[
"run.tcl"
,
".Xil"
,
"*.jou"
,
"*.log"
,
"*.pb"
,
"$(PROJECT).cache"
,
"$(PROJECT).data"
,
"work"
,
...
...
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