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Hdlmake
Commit ec10c20b authored by Javier D. Garcia-Lasheras's avatar Javier D. Garcia-Lasheras
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Add VHDL and Verilog template files support to Vivado

parent 92c32a9f
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Showing with 14 additions and 2 deletions
hdlmake/srcfile.py
View file @ ec10c20b
...@@ -182,6 +182,16 @@ class RAMFile(File): ...@@ -182,6 +182,16 @@ class RAMFile(File):
pass pass
class VHOFile(File):
"""Xilinx VHDL Template File"""
pass
class VEOFile(File):
"""Xilinx Verilog Template File"""
pass
class XCIFile(File): class XCIFile(File):
"""Xilinx Core IP File""" """Xilinx Core IP File"""
pass pass
...@@ -202,6 +212,8 @@ XILINX_FILE_DICT = { ...@@ -202,6 +212,8 @@ XILINX_FILE_DICT = {
'coe': COEFile, 'coe': COEFile,
'mif': MIFFile, 'mif': MIFFile,
'ram': RAMFile, 'ram': RAMFile,
'vho': VHOFile,
'veo': VEOFile,
'xci': XCIFile} 'xci': XCIFile}
......
hdlmake/tools/vivado.py
View file @ ec10c20b
...@@ -29,7 +29,7 @@ from .xilinx import ToolXilinx ...@@ -29,7 +29,7 @@ from .xilinx import ToolXilinx
from .make_sim import ToolSim from .make_sim import ToolSim
from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile, from hdlmake.srcfile import (XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile, XCOFile, COEFile, BDFile, TCLFile,
MIFFile, RAMFile) MIFFile, RAMFile, VHOFile, VEOFile)
class ToolVivado(ToolXilinx, ToolSim): class ToolVivado(ToolXilinx, ToolSim):
...@@ -48,7 +48,7 @@ class ToolVivado(ToolXilinx, ToolSim): ...@@ -48,7 +48,7 @@ class ToolVivado(ToolXilinx, ToolSim):
SUPPORTED_FILES = [XDCFile, XCIFile, NGCFile, XMPFile, SUPPORTED_FILES = [XDCFile, XCIFile, NGCFile, XMPFile,
XCOFile, COEFile, BDFile, TCLFile, XCOFile, COEFile, BDFile, TCLFile,
MIFFile, RAMFile] MIFFile, RAMFile, VHOFile, VEOFile]
CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb", CLEAN_TARGETS = {'clean': ["run.tcl", ".Xil", "*.jou", "*.log", "*.pb",
"$(PROJECT).cache", "$(PROJECT).data", "work", "$(PROJECT).cache", "$(PROJECT).data", "work",
......
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