Implemented feature 1337: Ignore verilog code between "pragma protect being_protected" and "pragma protect end_protected"

Make the code cleaner and less likely to break in the future.

Instances can be created without generic maps or port maps, in the form LABEL : entity. The existing regex captures these, but also finds false positives in component, record, and function definition sections, such as generic_name : natrual. new_dep_solver then compains that work.natural is not satisfied by any source file.
This commit creates regex patterns for component, function, and record definitions to remove them from the input buffer strings. The buf variable is reassigned after each re.sub call, to affect the removal.
Replacement strings are added to the buf, when a regex has matched - to help with debugging.
Finally, re.subn() replaced with re.sub() for simplicity.

For the case when the entity and architecture are in different files (because you have multiple architectures). Added architecture dependency type. Now architectures depend on entities, instances depend on architectures. Dependency key is only library.entity so will probably not work if analysing multiple architectures for an entity.

List files in compile order.
Tidy up.

Add vendor dependent files to the parsed synthesis fileset: WARNING, this breaks other synthesis tools but ISE!