Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Repository
427aa7bdefd60c83ebcb69cd535d60987d250886
Switch branch/tag
hdl-make
tests
counter
sim
modelsim
History
Find file
Select Archive Format
Source code
Download zip
Download tar.gz
Download tar.bz2
Download tar
Disable optimisations in order to have visibility of counter's signal.
· aabe6c84
Adrian Fiergolski
authored
Oct 10, 2014
aabe6c84
Name
Last commit
Last update
..
verilog
Loading commit data...
vhdl
Loading commit data...
vsim.do
Loading commit data...