Commit 6710cc6e authored by David Cussans's avatar David Cussans

Making a copy of IPBus into local respository

parent b5df7685
Copy of IPBus taken from
http://svn.cern.ch/guest/cactus/tags/ipbus_fw/ipbus_2_0_v1/firmware
modules = { "local" : ["./ethernet/cfg" , "ipbus_core/cfg", "slaves/cfg" ] }
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
files = [
"../../ethernet/coregen/tri_mode_eth_mac_v5_4.xco",
"../../ethernet/coregen/gig_eth_pcs_pma_v11_4.xco",
"../hdl/eth_s6_1000basex.vhd",
"../hdl/emac_hostbus_decl.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd" ,
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd",
"../../../../work/ipcore_dir/gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd"
]
# "../../ethernet/coregen/coregen/tri_mode_eth_mac_v5_4.xco",
# "../../ethernet/coregen/coregen/gig_eth_pcs_pma_v11_4.xco",
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
include ipbus/firmware/ethernet/cfg/file_list_gig_eth_pcs_pma_v11_4
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_transceiver_A.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/transceiver/gig_eth_pcs_pma_v11_4_s6_gtpwizard_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_5.xco
wcore ipbus/firmware/ethernet/coregen/gtwizard_v2_5_gbe_gtx.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex_new.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_kc705.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_sync_block.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_reset_sync.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_init.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_tx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_rx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gtx/example_design/gtwizard_v2_5_gbe_gtx_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gtx.vhd
ghdl gtwizard_v2_5_gbe_gtx_gt.vhd
# Ethernet setup for minit_240_ipb
core ipbus/firmware/ethernet/coregen/v5_emac_v1_8_serdes.xco
hdl ipbus/firmware/ethernet/hdl/eth_v5_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X_ch1.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_1000basex.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
include ipbus/firmware/ethernet/cfg/file_list_gig_eth_pcs_pma_v11_4
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
hdl ipbus/firmware/ethernet/hdl/eth_s6_gmii.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_4.xco
core ipbus/firmware/ethernet/coregen/mac_fifo_axi4.xco
# Xilinx ISE setup fragment for v5_emac_v1_8
# This is the ISE 14.3 version
hdl ipbus/firmware/ethernet/hdl/eth_v5_gmii.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8/v5_emac_v1_8.vhd
core ipbus/firmware/ethernet/coregen/mac_fifo.xco
# Virtex-6 1000basex setup
hdl ipbus/firmware/ethernet/hdl/eth_v6_basex.vhd
core ipbus/firmware/ethernet/coregen/v6_emac_v2_3_basex.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
#hdl ipbus/firmware/ethernet/gen_hdl/v6_emac_v2_3_basex/v6_emac_v2_3_basex_block.vhd
ghdl v6_emac_v2_3_basex/example_design/v6_emac_v2_3_basex_block.vhd
ghdl v6_emac_v2_3_basex/example_design/common/reset_sync.vhd
ghdl v6_emac_v2_3_basex/example_design/common/sync_block.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard_top.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/v6_gtxwizard_gtx.vhd
ghdl v6_emac_v2_3_basex/example_design/physical/double_reset.vhd
hdl ipbus/firmware/ethernet/hdl/eth_v6_sgmii.vhd
core ipbus/firmware/ethernet/coregen/v6_emac_v2_3_sgmii.xco
hdl ipbus/firmware/ethernet/gen_hdl/v6_emac_v2_3_sgmii/v6_emac_v2_3_sgmii_block.vhd
ghdl v6_emac_v2_3_sgmii/example_design/common/reset_sync.vhd
ghdl v6_emac_v2_3_sgmii/example_design/common/sync_block.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard_top.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/v6_gtxwizard_gtx.vhd
ghdl v6_emac_v2_3_sgmii/example_design/physical/double_reset.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_4
# This is the ISE 14.3 version modified for a v7 '490 production part
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_4/gig_eth_pcs_pma_v11_4_transceiver.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_reset_sync.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_init.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_gt.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_tx_startup_fsm.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_rx_startup_fsm.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gtwizard_v2_3_gbe/gtwizard_v2_3_gbe_recclk_monitor.vhd
ghdl gig_eth_pcs_pma_v11_4/example_design/gig_eth_pcs_pma_v11_4_sync_block.vhd
# Xilinx ISE setup fragment for gig_eth_pcs_pma_v11_5
# This is the ISE 14.3 version modified for a v7 '490 production part
core ipbus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_5.xco
wcore ipbus/firmware/ethernet/coregen/gtwizard_v2_5_gbe_gth.xco
core ipbus/firmware/ethernet/coregen/tri_mode_eth_mac_v5_5.xco
hdl ipbus/firmware/ethernet/hdl/eth_7s_1000basex_gth.vhd
hdl ipbus/firmware/ethernet/hdl/emac_hostbus_decl.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_block.vhd
hdl ipbus/firmware/ethernet/gen_hdl/gig_eth_pcs_pma_v11_5/gig_eth_pcs_pma_v11_5_transceiver_gth.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_reset_sync.vhd
ghdl gig_eth_pcs_pma_v11_5/example_design/gig_eth_pcs_pma_v11_5_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_init.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_tx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_rx_startup_fsm.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_sync_block.vhd
ghdl gtwizard_v2_5_gbe_gth.vhd
ghdl gtwizard_v2_5_gbe_gth_gt.vhd
ghdl gtwizard_v2_5_gbe_gth/example_design/gtwizard_v2_5_gbe_gth_gtrxreset_seq.vhd
# Xilinx ISE setup fragment for v5_emac_v1_8
# This is the ISE 14.3 version
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes_block.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/v5_emac_v1_8_serdes.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/gtx_dual_1000X.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx.vhd
xfile add firmware/ipbus/firmware/ethernet/gen_hdl/v5_emac_v1_8_serdes/rocketio_wrapper_gtx_tile.vhd
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="172" delta="old" >Generating IP...
</msg>
<msg type="warning" file="sim" num="100" delta="old" >The Simulation File Type &lt;<arg fmt="%s" index="1">Behavioral</arg>&gt; is not valid for this core. Overriding with File Type &lt;<arg fmt="%s" index="2">Structural</arg>&gt;.
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">A core named &apos;gig_eth_pcs_pma_v11_4&apos; already exists in the project. Output products for this core may be overwritten.</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;gig_eth_pcs_pma_v11_4&apos;...</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-iobuf&apos; found multiple times. Only the first occurence is considered.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">BlackBox generator run option &apos;-p&apos; found multiple times. Only the first occurence is considered.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">VHDL simulation file type &apos;Behavioral&apos; is not valid for this core. Overriding with simulation file type &apos;Structural&apos;.</arg>
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Overwriting existing file /projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pcs-pma.pdf with file from view xilinx_documentation</arg>
</msg>
<msg type="info" file="sim" num="949" delta="old" >Finished generation of ASY schematic symbol.
</msg>
<msg type="info" file="sim" num="948" delta="old" >Finished FLIST file generation.
</msg>
</messages>
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/firmware/ethernet/coregen/gig_eth_pcs_pma_v11_4.vhd&quot; into library work</arg>
</msg>
</messages>
INFO:sim:172 - Generating IP...
WARNING:sim:100 - The Simulation File Type <Behavioral> is not valid for this
core. Overriding with File Type <Structural>.
Applying current project options...
Finished applying current project options.
Resolving generics for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
WARNING:sim - A core named 'gig_eth_pcs_pma_v11_4' already exists in the
project. Output products for this core may be overwritten.
Applying external generics to 'gig_eth_pcs_pma_v11_4'...
Delivering associated files for 'gig_eth_pcs_pma_v11_4'...
Delivering EJava files for 'gig_eth_pcs_pma_v11_4'...
Generating implementation netlist for 'gig_eth_pcs_pma_v11_4'...
INFO:sim - Pre-processing HDL files for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - BlackBox generator run option '-iobuf' found multiple times. Only
the first occurence is considered.
WARNING:sim - BlackBox generator run option '-p' found multiple times. Only the
first occurence is considered.
Running synthesis for 'gig_eth_pcs_pma_v11_4'
Running ngcbuild...
Writing VHO instantiation template for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - VHDL simulation file type 'Behavioral' is not valid for this core.
Overriding with simulation file type 'Structural'.
Writing VHDL structural simulation model for 'gig_eth_pcs_pma_v11_4'...
WARNING:sim - Overwriting existing file
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus
/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4/doc/pg047-gig-eth-pc
s-pma.pdf with file from view xilinx_documentation
Delivered 2 files into directory
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4
Generating ASY schematic symbol...
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'gig_eth_pcs_pma_v11_4'...
Generating metadata file...
Generating ISE project...
XCO file found: gig_eth_pcs_pma_v11_4.xco
XMDF file found: gig_eth_pcs_pma_v11_4_xmdf.tcl
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.asy -view all -origin_type
imported
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc -view all -origin_type
created
Checking file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" for project device
match ...
File
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/f
irmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.ngc" device information
matches project device.
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.sym -view all -origin_type
imported
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd -view all -origin_type
created
INFO:HDLCompiler:1061 - Parsing VHDL file
"/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBu
s/firmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vhd" into library
work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/projects/HEP_Instrumentation/cad/designs/uob-hep-pc049a/trunk/firmware/IPBus/fi
rmware/ethernet/coregen/tmp/_cg/gig_eth_pcs_pma_v11_4.vho -view all -origin_type
imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
Please set the new top explicitly by running the "project set top" command.
To re-calculate the new top automatically, set the "Auto Implementation Top"
property to true.
Top level has been set to "/gig_eth_pcs_pma_v11_4"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'gig_eth_pcs_pma_v11_4'.
##############################################################
#
# Xilinx Core Generator version 14.3
# Date: Fri Feb 1 20:38:42 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:tri_mode_eth_mac:5.4
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx485t
SET devicefamily = virtex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1927
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Tri_Mode_Ethernet_MAC xilinx.com:ip:tri_mode_eth_mac:5.4
# END Select
# BEGIN Parameters
CSET component_name=emac_serdes_5_4
CSET enable_avb=false
CSET frame_filter=false
CSET half_duplex=false
CSET mac_speed=1000_Mbps
CSET management_interface=false
CSET number_of_table_entries=0
CSET physical_interface=Internal
CSET statistics_counters=false
CSET statistics_reset=true
CSET statistics_width=64bit
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-06-05T21:10:47Z
# END Extra information
GENERATE
# CRC: 842dc3da
##############################################################
#
# Xilinx Core Generator version 13.4
# Date: Sat Aug 4 10:37:18 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:gig_eth_pcs_pma:11.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7vx485t
SET devicefamily = virtex7
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ffg1927
SET removerpms = false
SET simulationfiles = Structural
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Ethernet_1000BASE-X_PCS/PMA_or_SGMII xilinx.com:ip:gig_eth_pcs_pma:11.2
# END Select
# BEGIN Parameters
CSET auto_negotiation=false
CSET component_name=eth_pcspma_basex_11_2
CSET management_interface=false
CSET physical_interface=Transceiver
CSET sgmii_mode=10_100_1000
CSET sgmii_phy_mode=false
CSET standard=1000BASEX
CSET timing_sim=false
CSET transceiver_tile=A
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-30T08:06:39Z
# END Extra information
GENERATE
# CRC: 4f9939d3
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "gig_eth_pcs_pma_v11_4" xc6slx100t-3fgg484 VHDL CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result
##
## Core Generator Run Script, generator for Project Navigator regen command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_regen "tri_mode_eth_mac_v5_4" xc6slx100t-3fgg484 VHDL CURRENT ]
if { $result == 0 } {
puts "Core Generator regen command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator regen command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator regen cancelled."
}
exit $result
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 gig_eth_pcs_pma_v11_4
RECTANGLE Normal 32 32 544 1152
LINE Normal 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName reset
PINATTR Polarity IN
LINE Normal 0 176 32 176 <