added comments

0cea86ef · Evangelia Gousiou · b6f02ae3 · 0cea86ef · 0cea86ef · 0cea86ef
Commit 0cea86ef authored Feb 21, 2017 by Evangelia Gousiou
5 changed files
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
@@ -39,7 +39,7 @@
 --               |________________________________________________________________|               |
 --                             Figure 1: fmc_masterFIP_core architecture                          |
 --                                                                                                |
--              MrFIP WBGEN2 CSR:                                                                 |
+--              MASTERFIP WBGEN2 CSR:                                                             |
 --              The mrfip_wbgen2_csr module has been generated through the wbgen2 application.    |
 --              It establishes the interface with the processor, usually a Mock Turtle core.      |
 --              This interface contains a set of control and status registers for each one of the |
@@ -65,7 +65,7 @@
 --               - copies all the payload registers (tx_payld_ctrl, tx_payld_reg1..tx_payld_reg67)|
 --                 and the register that indicates the number of payload bytes to                 |
 --                 serialize (tx_ctrl_bytes_num)                                                  |
--               - starts serializing a WorldFIP frame (see following figure). Note that the FSS, |
+--               - starts serializing a WorldFIP frame (see following Figure). Note that the FSS, |
 --                 CRC and FES fields are generated internally in the masterfip_tx unit.          |
 --               - after the FES, rises the tx_stat_stop status bit to signal the MT for the end  |
 --                 of a successful frame transmission.                                            |
@@ -102,26 +102,26 @@
 --                                                                                                |
 --              <---2 bytes--><-1byte-><------  rx_ctrl_bytes_num  -------><--2 bytes--><-1byte-> |
 --                                                                                                |
--                                    Figure 2: WorldFIP rx frame structure                       |
+--                                    Figure 3: WorldFIP rx frame structure                       |
 --                                                                                                |
 --              EXT SYNC PULSE:                                                                   |
 --              The modules regarding the ext_sync_pulse are synchronising, deglitching and       |
 --              counting the number of rising-edge pulses that are arriving to the ext_sync input |
--              of the board and provide the result to the dedicated masterfip_wbgen2_csr register|
+--              of the board and provide the result to a dedicated masterfip_wbgen2_csr register. |
 --                                                                                                |
 --              MACROCYCLE:                                                                       |
 --              The modules regarding the macrocycle are counting the time of a macrocycle using  |
 --              the 10 ns input clock as well as the number of macrocycles since startup/a reset. |
 --              Dedicated registers in the masterfip_wbgen2_csr provide the counters values       |
 --              to the processor (MT). Note that the macrocycle length comes from the processor   |
--              through a dedicated register in the masterfip_wbgen2_csr and should be set once   |
+--              through another dedicated register in the masterfip_wbgen2_csr and should be set  |
--              in the application startup.                                                       |
+--              once in the application startup.                                                  |
 --                                                                                                |
 --              TURNAROUND, SILENCE TIMES:                                                        |
 --              The modules regarding the turnaround and silence time are counting the respective |
 --              time using the 10 ns clock. Dedicated regs in the masterfip_wbgen2_csr provide    |
 --              the counters values to the processor (MT). As in the case of the macrocycle length|
--              the turnaround and silence time length is provided through dedicated registers in |
+--              the turnaround and silence time length is provided through other dedicated regs in|
 --              the masterfip_wbgen2_csr that should be set once in the application startup.      |
 --                                                                                                |
 --              ONEWIRE:                                                                          |

--- a/rtl/masterFIP_pkg.vhd
+++ b/rtl/masterFIP_pkg.vhd
--- a/rtl/masterfip_tx.vhd
+++ b/rtl/masterfip_tx.vhd
@@ -33,7 +33,7 @@
 --              o TX OSC          this unit comes unmodified from the nanoFIP project.            |
 --                                It generates the output FD_TXCK as well as an array of pulses,  |
 --                                tx_sched_p_buff, used for the synchronization of the            |
--                                TX SERIALIZER's actions.                                     |
+--                                TX SERIALIZER's actions.                                        |
 --                                                                                                |
 --              o DATA RETRIEVAL  this unit copies the bytes provided by the processor (MT)       |
 --                                upon the activation of the signal tx_start.                     |

--- a/rtl/wf_package.vhd
+++ b/rtl/wf_package.vhd
 --_________________________________________________________________________________________________
 --                                                                                                |
--                                         |The nanoFIP|                                          |
+--                                       |masterFIP core|                                         |
 --                                                                                                |
 --                                         CERN,BE/CO-HT                                          |
 --________________________________________________________________________________________________|
@@ -12,9 +12,18 @@
 ---------------------------------------------------------------------------------------------------
 -- File         wf_package.vhd                                                                    |
 --                                                                                                |
-- Description  Definitions of constants, types, entities, functions                              |
+-- Description  Definitions of constants, types, entities, functions related to WorldFIP          |
-- Author       Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
+--              serialization and deserialization; the package is essential for all the modules   |
-- Date         02/2016                                                                        |
+--              coming from the nanoFIP design.                                                   |
+--              As in the masterFIP design the clk is 100 MHz and in the nanoFIP 40 MHz it was    |
+--              needed to have a new wf_package. In principle the nanoFIP design could have been  |
+--              modified to accept generics rather than constants, however as it is a stable      |
+--              design it was decided to keep it as it is and use for synthesis this package      |
+--              rather than the one coming with the nanoFIP submodule.                            |
+--              A different package, the masterfip_pkg is used in the masterfip design for all    |
+--              other topics, not related to the WorldFIP serialization/ deserialization.         |
+--                                                                                                |
+-- Authors      Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)                                 |
 ---------------------------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------------------------
@@ -50,33 +59,34 @@ package wf_package is
 ---------------------------------------------------------------------------------------------------
--                               Constant regarding the user clock                               --
+--                             Constants regarding the system clock                              --
 ---------------------------------------------------------------------------------------------------
-- 10ns clock for the masterFIP_core; same for the CPUs 
+-- 10ns clock for the masterFIP_core; same for the CPUs
-  constant c_QUARTZ_PERIOD_NS : real    := 10.0;
+  constant c_QUARTZ_PERIOD_NS    : real    := 10.0;
-  constant c_QUARTZ_FREQ_MHZ  : real    := 100.0;
+  constant c_QUARTZ_FREQ_MHZ     : real    := 100.0;
  constant c_QUARTZ_FREQ_MHZ_INT : integer := 100;
-  constant c_1SEC_CNT_LGTH    : natural := 27;
+  constant c_1SEC_CNT_LGTH  : natural  := 27; -- lgth of counter that counts 1 sec using the sys clk
-  constant c_1SEC_CLK_TICKS   : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
+  constant c_1SEC_CLK_TICKS : unsigned := to_unsigned((1000000000 / integer(c_QUARTZ_PERIOD_NS)),
                                                                                  c_1SEC_CNT_LGTH);
 ---------------------------------------------------------------------------------------------------
 --                       Constants regarding the session timeout counters                        --
 ---------------------------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------------------------
-- To add a robust layer of protection to the FSMs of the design, counters that depend only on
+-- To add a robust layer of protection to the FSMs of the design (WorldFIP serializer and
-- the system clock have being implemented; when they are filled up, they can bring the FSMs back
+-- deserializer), counters that depend only on the system clock have being implemented; when they
-- to the IDLE state.
+-- are filled up, they can bring the FSMs back to the IDLE state.
 -- For the wf_rx_deserializer/wf_tx_serializer at the slowest bit rate, 31.25 kbps, the
-- reception/transmission of the longest frame takes:
+-- reception/transmission of the longest frame takes: 268 bytes RP_DAT = 68608 us
-- 268 bytes RP_DAT = 68608 us
 -- This demands for a 23 bits counter.
-- This for example means that if after 83 ms the reception/transmission of a frame has not been
+-- This means that if after 83 ms the reception/transmission of a frame has not been completed,
-- completed, the respective FSMs will be reset.
+-- the respective FSMs will be reset.
  constant c_SESSION_TIMEOUT_C_LGTH : natural := 23; -- 83 ms
@@ -84,7 +94,6 @@ package wf_package is
 ---------------------------------------------------------------------------------------------------
 --                             Constant regarding the deglitch filter                            --
 ---------------------------------------------------------------------------------------------------
  constant c_DEGLITCH_THRESHOLD : natural := 10;
@@ -99,7 +108,6 @@ package wf_package is
 ---------------------------------------------------------------------------------------------------
 --                     Constants regarding the the ID_DAT and RP_DAT frame structure             --
 ---------------------------------------------------------------------------------------------------
  constant c_VP   : std_logic_vector (1 downto 0) := "11";
  constant c_VN   : std_logic_vector (1 downto 0) := "00";
  constant c_ONE  : std_logic_vector (1 downto 0) := "10";
@@ -114,14 +122,12 @@ package wf_package is
 ---------------------------------------------------------------------------------------------------
 --                               Constant regarding the Transmitter                              --
 ---------------------------------------------------------------------------------------------------
  constant c_TX_SCHED_BUFF_LGTH : natural := 4; -- length of the buffer of pulses used for
                                                -- the transmission synchronization
 ---------------------------------------------------------------------------------------------------
 --                 Constants regarding the position of bytes in the frame structure              --
 ---------------------------------------------------------------------------------------------------
  constant c_CTRL_BYTE_INDEX     : std_logic_vector (7 downto 0) := "00000000"; -- 0
  constant c_PDU_BYTE_INDEX      : std_logic_vector (7 downto 0) := "00000001"; -- 1
  constant c_LGTH_BYTE_INDEX     : std_logic_vector (7 downto 0) := "00000010"; -- 2
@@ -132,8 +138,7 @@ package wf_package is
 ---------------------------------------------------------------------------------------------------
 --                           Constants & Types regarding the bit rate                            --
 ---------------------------------------------------------------------------------------------------
+-- Calculation of the number of clk ticks equivalent to the reception/ transmission period
-  -- Calculation of the number of uclk ticks equivalent to the reception/ transmission period
  constant c_PERIODS_COUNTER_LGTH : natural := 12; -- in the slowest bit rate (31.25kbps), the
                                                   -- period is 32000 ns and can be measured after

--- a/top/spec/spec_masterfip_mt.vhd
+++ b/top/spec/spec_masterfip_mt.vhd