Skip to content

M
MasterFIP - Gateware
Commit 3c5faced authored by Evangelia Gousiou's avatar Evangelia Gousiou
Browse files
Options

- added DAC SPI for the 25MHz OSC1 of the SPEC (mainly to be able to set it to… 

- added DAC SPI for the 25MHz OSC1 of the SPEC (mainly to be able to set it to the middle range where the OSC stability is maximum)
- added corresponding reg in fmc_masterfip_csr.wb
- cleanup of testbench
parent 9aa29601
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 5858 additions and 1656 deletions
rtl/fmc_masterFIP_core.vhd
View file @ 3c5faced
...@@ -159,27 +159,32 @@ entity fmc_masterFIP_core is ...@@ -159,27 +159,32 @@ entity fmc_masterFIP_core is
adc_5v_en_n_o : out std_logic; adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic; adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic; adc_sec_conn_n_o : out std_logic;
-- DAC configuration (to set OSC1 to its middle range where the stability is max)
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
-- FielDrive -- FielDrive
fd_rxcdn_i : in std_logic; fd_rxcdn_i : in std_logic;
fd_rxd_i : in std_logic; fd_rxd_i : in std_logic;
fd_txer_i : in std_logic; fd_txer_i : in std_logic;
fd_wdgn_i : in std_logic; fd_wdgn_i : in std_logic;
fd_rstn_o : out std_logic; fd_rstn_o : out std_logic;
fd_txck_o : out std_logic; fd_txck_o : out std_logic;
fd_txd_o : out std_logic; fd_txd_o : out std_logic;
fd_txena_o : out std_logic; fd_txena_o : out std_logic;
-- WISHBONE classic bus interface -- WISHBONE classic bus interface
wb_adr_i : in std_logic_vector(g_span-1 downto 0); wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0); wb_dat_i : in std_logic_vector(g_width-1 downto 0);
wb_stb_i : in std_logic; wb_stb_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0); wb_sel_i : in std_logic_vector(3 downto 0);
wb_we_i : in std_logic; wb_we_i : in std_logic;
wb_cyc_i : in std_logic; wb_cyc_i : in std_logic;
wb_stall_o : out std_logic; wb_stall_o : out std_logic;
wb_ack_o : out std_logic; wb_ack_o : out std_logic;
wb_dat_o : out std_logic_vector(g_width-1 downto 0); wb_dat_o : out std_logic_vector(g_width-1 downto 0);
-- Aux -- Aux
aux_o : out std_logic_vector(7 downto 0)); -- group of 8 aux signals to pass to the higher levels aux_o : out std_logic_vector(7 downto 0)); -- group of 8 aux signals to pass to the higher levels
...@@ -233,8 +238,13 @@ architecture rtl of fmc_masterFIP_core is ...@@ -233,8 +238,13 @@ architecture rtl of fmc_masterFIP_core is
signal fd_txer_cnt : std_logic_vector(31 downto 0); signal fd_txer_cnt : std_logic_vector(31 downto 0);
-- ADC -- ADC
signal adc_sec_conn_n, adc_prim_conn_n : std_logic; signal adc_sec_conn_n, adc_prim_conn_n : std_logic;
-- DAC
signal dac_value : std_logic_vector(15 downto 0);
signal dac_load, dac_load_p : std_logic;
-- ext_sync -- ext_sync
signal ext_sync, ext_sync_filt : std_logic;
signal ext_sync_tst_n : std_logic; signal ext_sync_tst_n : std_logic;
signal ext_sync_di : std_logic_vector(0 downto 0);
-- LEDs -- LEDs
signal sync_led, out_of_sync_led : std_logic; signal sync_led, out_of_sync_led : std_logic;
-- debug -- debug
...@@ -304,6 +314,9 @@ begin ...@@ -304,6 +314,9 @@ begin
mf_ext_sync_tst_n_o => ext_sync_tst_n, mf_ext_sync_tst_n_o => ext_sync_tst_n,
mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst, mf_ext_sync_p_cnt_rst_o => ext_sync_p_cnt_host_rst,
mf_ext_sync_p_cnt_i => ext_sync_p_cnt, mf_ext_sync_p_cnt_i => ext_sync_p_cnt,
-- DAC configuration
mf_dac_config_value_o => dac_value,
mf_dac_config_load_o => dac_load,
-- bus speed -- bus speed
mf_speed_i(1) => speed_b1_i, mf_speed_i(1) => speed_b1_i,
mf_speed_i(0) => speed_b0_i, mf_speed_i(0) => speed_b0_i,
...@@ -519,16 +532,34 @@ begin ...@@ -519,16 +532,34 @@ begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- external sync -- -- external sync --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- TODO: add antiglitch filter; maybe also disable the reception of a new pulse for some time after -- TODO: maybe also disable the reception of a new pulse for some time after the previous pulse
-- the previous pulse
-- synchronizer and edge detection -- input synchronizer
cmp_ext_sync_sync: gc_sync_register
generic map(g_width => 1)
port map
(clk_i => clk_i,
rst_n_a_i => core_rst_n,
d_i => ext_sync_di,
q_o(0) => ext_sync);
ext_sync_di(0) <= ext_sync_i; -- d_i is std_logic_vector; in our case there is only 1 bit
-- deglitch filter
cmp_ext_sync_glitch_filt: gc_glitch_filt
generic map(g_len => 10) -- glitches up to 100ns are ignored;
port map -- Note that the filter adds a 100ns delay to the ext_sync signal
(clk_i => clk_i,
rst_n_i => core_rst_n,
dat_i => ext_sync,
dat_o => ext_sync_filt);
-- edge detection
cmp_ext_sync_p_detect: gc_sync_ffs cmp_ext_sync_p_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map port map
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => core_rst_n, rst_n_i => core_rst_n,
data_i => ext_sync_i, data_i => ext_sync_filt,
ppulse_o => ext_sync_p); ppulse_o => ext_sync_p);
-- pulses counter -- pulses counter
...@@ -551,7 +582,7 @@ begin ...@@ -551,7 +582,7 @@ begin
-- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore -- the macrocyc_lgth is set slightly larger than the external synchronization period; therefore
-- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the -- th macrocycle counter should not be reaching zero; if it reaches zero, it means that the
-- external synchronization pulse did not arrive in time -- external synchronization pulse did not arrive in time
-- counter counting the macrocycle time -- counter counting the macrocycle time
cmp_macrocycle_time_cnt: decr_counter cmp_macrocycle_time_cnt: decr_counter
generic map(width => 31) generic map(width => 31)
...@@ -585,6 +616,8 @@ begin ...@@ -585,6 +616,8 @@ begin
counter_o => num_of_macrocyc_cnt); counter_o => num_of_macrocyc_cnt);
num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full; num_of_macrocyc_cnt_reinit <= core_rst_n or num_of_macrocyc_cnt_full;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- turnaround counter -- -- turnaround counter --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -818,7 +851,7 @@ begin ...@@ -818,7 +851,7 @@ begin
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
data_i => fd_wdgn_i, data_i => fd_wdgn_i,
ppulse_o => fd_wdgn_p); ppulse_o => fd_wdgn_p);
-- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle -- process that registers the macrocycle_cnt value upon the last fd_wdgn_p of a macrocycle
p_fd_wdgn_capture : process(clk_i) p_fd_wdgn_capture : process(clk_i)
...@@ -844,7 +877,7 @@ begin ...@@ -844,7 +877,7 @@ begin
(clk_i => clk_i, (clk_i => clk_i,
rst_n_i => rst_n, rst_n_i => rst_n,
data_i => fd_txer_i, data_i => fd_txer_i,
ppulse_o => fd_txer_p); ppulse_o => fd_txer_p);
-- counter counting the number of fd_wdgn_p -- counter counting the number of fd_wdgn_p
cmp_fd_wdgn_cnt:incr_counter cmp_fd_wdgn_cnt:incr_counter
...@@ -857,7 +890,7 @@ begin ...@@ -857,7 +890,7 @@ begin
counter_o => fd_txer_cnt); counter_o => fd_txer_cnt);
fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0' fd_txer_cnt_reinit <= '1' when core_rst_n = '0' or macrocyc_load_p = '1' or fd_host_rstn = '0'
else '0'; else '0';
-- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle -- process that registers the macrocycle_cnt value upon the last fd_txer_p of a macrocycle
p_fd_txer_capture : process(clk_i) p_fd_txer_capture : process(clk_i)
...@@ -875,9 +908,40 @@ begin ...@@ -875,9 +908,40 @@ begin
end if; end if;
end process; end process;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- LEDs -- -- DAC --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
cmp_dac_config : spec_serial_dac_arb
generic map
(g_invert_sclk => false,
g_num_extra_bits => 8)
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
val1_i => dac_value,
load1_i => dac_load_p,
val2_i => (others => '0'),
load2_i => '0',
dac_cs_n_o(0) => dac_cs_n_o(0),
dac_cs_n_o(1) => dac_cs_n_o(1),
-- dac_clr_n_o => open,
dac_sclk_o => dac_sclk_o,
dac_din_o => dac_din_o);
-- edge detection on the dac_value signal
cmp_dac_value_pulse_detect: gc_sync_ffs
generic map(g_sync_edge => "positive")
port map
(clk_i => clk_i,
rst_n_i => core_rst_n,
data_i => dac_load,
ppulse_o => dac_load_p);
---------------------------------------------------------------------------------------------------
-- LEDs --
---------------------------------------------------------------------------------------------------
cmp_out_of_sync_led: gc_extend_pulse cmp_out_of_sync_led: gc_extend_pulse
generic map generic map
(g_width => 1000000) (g_width => 1000000)
...@@ -897,7 +961,7 @@ begin ...@@ -897,7 +961,7 @@ begin
pulse_i => ext_sync_p, pulse_i => ext_sync_p,
extended_o => sync_led); extended_o => sync_led);
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- aux -- -- aux --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
......
rtl/fmc_masterfip_csr.vhd
View file @ 3c5faced
This diff is collapsed.
rtl/masterFIP_pkg.vhd
View file @ 3c5faced
...@@ -204,6 +204,9 @@ package masterFIP_pkg is ...@@ -204,6 +204,9 @@ package masterFIP_pkg is
mf_adc_prim_conn_n_o : out std_logic; mf_adc_prim_conn_n_o : out std_logic;
mf_adc_sec_conn_n_o : out std_logic; mf_adc_sec_conn_n_o : out std_logic;
mf_dac_config_value_o : out std_logic_vector(15 downto 0);
mf_dac_config_load_o : out std_logic;
mf_ext_sync_term_en_o : out std_logic; mf_ext_sync_term_en_o : out std_logic;
mf_ext_sync_dir_o : out std_logic; mf_ext_sync_dir_o : out std_logic;
mf_ext_sync_oe_o : out std_logic; mf_ext_sync_oe_o : out std_logic;
...@@ -412,6 +415,9 @@ package masterFIP_pkg is ...@@ -412,6 +415,9 @@ package masterFIP_pkg is
adc_5v_en_n_o : out std_logic; adc_5v_en_n_o : out std_logic;
adc_prim_conn_n_o : out std_logic; adc_prim_conn_n_o : out std_logic;
adc_sec_conn_n_o : out std_logic; adc_sec_conn_n_o : out std_logic;
dac_cs_n_o : out std_logic_vector(1 downto 0);
dac_sclk_o : out std_logic;
dac_din_o : out std_logic;
aux_o : out std_logic_vector(7 downto 0); aux_o : out std_logic_vector(7 downto 0);
wb_adr_i : in std_logic_vector(g_span-1 downto 0); wb_adr_i : in std_logic_vector(g_span-1 downto 0);
wb_dat_i : in std_logic_vector(g_width-1 downto 0); wb_dat_i : in std_logic_vector(g_width-1 downto 0);
......
rtl/wbgen/fmc_masterfip_csr.h
View file @ 3c5faced
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.htm
View file @ 3c5faced
This diff is collapsed.
rtl/wbgen/fmc_masterfip_csr.wb
View file @ 3c5faced
...@@ -140,7 +140,36 @@ peripheral { ...@@ -140,7 +140,36 @@ peripheral {
}; };
-------------------------------------------------------------------------------
-- DAC configuration --
-------------------------------------------------------------------------------
reg {
name = "dac";
prefix = "dac_config";
field {
name = "value";
prefix = "value";
description = "Vout= Vref (value/ 65536)\
For the DAC middle range: value = 32768 = 0x8000";
type = SLV;
size = 16;
-- add reset value = "0x8000";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "load";
prefix = "load";
description = "upon rising edge, the value is transferred to the dac";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- external synch -- -- external synch --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
......
sim/spec/data_vectors/board_settings_config.txt
View file @ 3c5faced
...@@ -9,6 +9,6 @@ vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1) ...@@ -9,6 +9,6 @@ vcc -- m_id_0 can take the values (gnd, vcc, sd0, sd1)
1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1) 1 -- nostat: nanoFIP status enabled(0), nanoFIP status disabled(1)
000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101) 000 -- produced variable length: 2 bytes(000), 8 bytes(001), 16 bytes(010), 32 bytes(011), 64 bytes(100), 124 bytes(101)
01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10) 01 -- rate: 31.25 kbits(00), 1 Mbit(01), 2.5 Mbits(10)
0 -- mode (slone): memory mode(0), stand alone(1) 1 -- mode (slone): memory mode(0), stand alone(1)
03 -- station_adr (8-bit bus in hexadecimal format) 03 -- station_adr (8-bit bus in hexadecimal format)
20000 ms -- time for which the configuration above is valid 20000 ms -- time for which the configuration above is valid
sim/spec/data_vectors/masterFIP_test.vec
View file @ 3c5faced
...@@ -44,8 +44,8 @@ wait %d20 ...@@ -44,8 +44,8 @@ wait %d20
----- CHECK COUNTERS FUNCTINALITY ----- ----- CHECK COUNTERS FUNCTINALITY -----
-- macrocycle cnt start -- macrocycle cnt start
wr 000000000003001C F 80004880 --wr 000000000003001C F 80004880
wait %d20 --wait %d20
--wr 000000000003001C F 00002A6D --wr 000000000003001C F 00002A6D
-- turnar counter top -- turnar counter top
...@@ -60,111 +60,109 @@ wait %d20 ...@@ -60,111 +60,109 @@ wait %d20
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
-- tx_rst -- tx_rst
wr 0000000000030038 F 00000001 wr 000000000003003C F 00000001
wait %d10 wait %d10
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 0000000000030160 F 00000003 wr 000000000003016C F 00000003
wait %d20 wait %d20
-- data bytes varid = 0503 for agent to consume -- data bytes varid = 0503 for agent to consume
wr 0000000000030164 F 00000305 wr 0000000000030170 F 00000305
wait %d20 wait %d20
-- tx_start -- tx_start
wr 0000000000030038 F 00000202 wr 000000000003003C F 00000202
wait %d20000 wait %d20000
--------------- RP_DAT --------------- --------------- RP_DAT ---------------
-- tx_rst -- tx_rst
wr 0000000000030038 F 00000001 wr 000000000003003C F 00000001
wait %d10 wait %d10
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
wait %d20 wait %d20
-- control byte of rp_dat -- control byte of rp_dat
wr 0000000000030160 F 00000002 wr 000000000003016C F 00000002
wait %d20 wait %d20
-- data bytes -- data bytes
wr 0000000000030164 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940 wr 0000000000030170 F BBAA0340 -- for 2 data bytes: BBAA0340 | for 8 data bytes: BBAA0940
wait %d20 wait %d20
wr 0000000000030168 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC wr 0000000000030174 F EEDDCC05 -- for 2 data bytes: EEDDCC05 | for 8 data bytes: FFEEDDCC
-- tx_start -- tx_start
wr 0000000000030038 F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02 wr 000000000003003C F 00000502 -- for 2 data bytes: 00000502 | for 8 data bytes: 00000B02
wait %d40000 wait %d40000
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
-- tx_rst -- tx_rst
wr 0000000000030038 F 00000001 wr 000000000003003C F 00000001
wait %d10 wait %d10
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 0000000000030160 F 00000003 wr 000000000003016C F 00000003
wait %d20 wait %d20
-- data bytes varid = 1403 for agent to send identification -- data bytes varid = 1403 for agent to send identification
wr 0000000000030164 F 00000314 wr 0000000000030170 F 00000306 -------------------------0314
wait %d20 wait %d20
-- tx_start -- tx_start
wr 0000000000030038 F 00000202 wr 000000000003003C F 00000202
wait %d20 wait %d20
-- deactivate tx_start -- deactivate tx_start
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
-- release rx_rst -- release rx_rst
wr 0000000000030044 F 00000000 wr 0000000000030048 F 00000000
wait %d40000 wait %d40000
-- read received data -- read received data
rd 0000000000030050 F 00000002 rd 0000000000030054 F 00000002
wait %d20 wait %d20
rd 0000000000030044 F 03800550 rd 0000000000030048 F 03800550
wait %d40000 wait %d40000
--------------- ID_DAT --------------- --------------- ID_DAT ---------------
tx_rst tx_rst
wr 0000000000030038 F 00000001 wr 000000000003003C F 00000001
wait %d10 wait %d10
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
wait %d20 wait %d20
-- control byte of id_dat -- control byte of id_dat
wr 0000000000030160 F 00000003 wr 000000000003016C F 00000003
wait %d20 wait %d20
-- data bytes varid = 0603 for agent to produce -- data bytes varid = 0603 for agent to produce
wr 0000000000030164 F 00000306 wr 0000000000030168 F 00000306
wait %d20 wait %d20
-- tx_start -- tx_start
wr 0000000000030038 F 00000202 wr 000000000003003C F 00000202
wait %d20 wait %d20
-- deactivate tx_start -- deactivate tx_start
wr 0000000000030038 F 00000000 wr 000000000003003C F 00000000
-- release rx_rst -- release rx_rst
wr 0000000000030044 F 00000000 wr 0000000000030048 F 00000000
wait %d40000 wait %d40000
-- read received data -- read received data
rd 0000000000030050 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF rd 0000000000030054 F 00000000 FFFFFFFF -- XXXXXX02 FFFFFFFF
wait %d20
rd 0000000000030054 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20 wait %d20
rd 0000000000030058 F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF rd 0000000000030058 F 00000000 FFFFFFFF -- BC870940 FFFFFFFF
wait %d20 wait %d20
rd 000000000003005C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF rd 000000000003005C F 00000000 FFFFFFFF -- B07D75EF FFFFFFFF
wait %d20 wait %d20
rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF rd 0000000000030060 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20 wait %d20
...@@ -172,6 +170,8 @@ rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF ...@@ -172,6 +170,8 @@ rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20 wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20 wait %d20
rd 0000000000030064 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20
rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF rd 0000000000030068 F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
wait %d20 wait %d20
rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF rd 000000000003006C F 00000000 FFFFFFFF -- XX05ABE9 FFFFFFFF
...@@ -236,7 +236,7 @@ wait %d40000 ...@@ -236,7 +236,7 @@ wait %d40000
--------------- RP_FIN --------------- --------------- RP_FIN ---------------
-- control byte of rp_fin -- control byte of rp_fin
wr 000000000003015C F 00000040 wr 000000000003016C F 00000040
wait %d20 wait %d20
-- rx_rst -- rx_rst
...@@ -244,5 +244,5 @@ wr 0000000000030048 F 00000001 ...@@ -244,5 +244,5 @@ wr 0000000000030048 F 00000001
wait %d20 wait %d20
-- tx_start -- tx_start
wr 0000000000030038 F 00000002 wr 000000000003003C F 00000002
wait %d20000 wait %d20000
\ No newline at end of file
sim/spec/data_vectors/user_sequence.txt
View file @ 3c5faced
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
0,1,8,0,0 -- reading VAR1 from memory 0,1,8,0,0 -- reading VAR1 from memory
350 us -- stand-by time 350 us -- stand-by time
1,3,8,0,0 -- writting VAR3 in memory 1,3,8,0,0 -- writting VAR3 in memory
20383 us -- stand-by time 20383 us -- stand-by time
1,3,124,0,0 -- writting VAR3 in memory 1,3,124,0,0 -- writting VAR3 in memory
431 us -- stand-by time 431 us -- stand-by time
......
sim/spec/testbench/nanoFIP_lib/wf_crc.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_decr_counter.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_decr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_decr_counter.vhd |
-- Description Decreasing counter with synchronous reset, load enable and decrease enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 10/2010 |
-- Version v0.01 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 10/2011 EG v0.01b nfip_rst_i renamed to counter_rst_i; counter_top renamed to |
-- counter_top_i; initial value after reset is all '1'; |
-- counter_decr_p_i renamed to counter_decr_i |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_decr_counter
--=================================================================================================
entity wf_decr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signal from the wf_reset_unit
counter_rst_i : in std_logic; -- resets counter to all '1'
-- Signals from any unit
counter_decr_i : in std_logic; -- decrement enable
counter_load_i : in std_logic; -- load enable; loads counter to counter_top_i
counter_top_i : in unsigned (g_counter_lgth-1 downto 0); -- load value
-- OUTPUTS
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_zero_o : out std_logic); -- empty counter indication
end entity wf_decr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_decr_counter is
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Decr_Counter
Decr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_rst_i = '1' then
s_counter <= (others => '1');
else
if counter_load_i = '1' then
s_counter <= counter_top_i;
elsif counter_decr_i = '1' then
s_counter <= s_counter - 1;
end if;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_zero_o <= '1' when s_counter = to_unsigned(0, s_counter'length) else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_incr_counter.vhd 0 → 100644
View file @ 3c5faced
--_________________________________________________________________________________________________
-- |
-- |The nanoFIP| |
-- |
-- CERN,BE/CO-HT |
--________________________________________________________________________________________________|
---------------------------------------------------------------------------------------------------
-- |
-- wf_incr_counter |
-- |
---------------------------------------------------------------------------------------------------
-- File wf_incr_counter.vhd |
-- Description Increasing counter with synchronous reinitialise and increase enable |
-- Authors Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 01/2011 |
-- Version v0.011 |
-- Depends on - |
---------------- |
-- Last changes |
-- 10/2010 EG v0.01 first version |
-- 01/2011 EG v0.011 counter_full became a constant |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE |
-- ------------------------------------ |
-- This source file is free software; you can redistribute it and/or modify it under the terms of |
-- the GNU Lesser General Public License as published by the Free Software Foundation; either |
-- version 2.1 of the License, or (at your option) any later version. |
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
-- See the GNU Lesser General Public License for more details. |
-- You should have received a copy of the GNU Lesser General Public License along with this |
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html |
---------------------------------------------------------------------------------------------------
--=================================================================================================
-- Libraries & Packages
--=================================================================================================
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
-- Specific library
library work;
use work.WF_PACKAGE.all; -- definitions of types, constants, entities
--=================================================================================================
-- Entity declaration for wf_incr_counter
--=================================================================================================
entity wf_incr_counter is
generic(g_counter_lgth : natural := 4); -- default length
port(
-- INPUTS
-- nanoFIP User Interface general signal
uclk_i : in std_logic; -- 40 MHz clock
-- Signals from any unit
counter_incr_i : in std_logic; -- increment enable
counter_reinit_i : in std_logic; -- reinitializes counter to 0
-- OUTPUT
-- Signal to any unit
counter_o : out unsigned (g_counter_lgth-1 downto 0); -- counter
counter_is_full_o : out std_logic); -- counter full indication
-- (all bits to '1')
end entity wf_incr_counter;
--=================================================================================================
-- architecture declaration
--=================================================================================================
architecture rtl of wf_incr_counter is
constant c_COUNTER_FULL : unsigned (g_counter_lgth-1 downto 0) := (others => '1');
signal s_counter : unsigned (g_counter_lgth-1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
---------------------------------------------------------------------------------------------------
-- Synchronous process Incr_Counter
Incr_Counter: process (uclk_i)
begin
if rising_edge (uclk_i) then
if counter_reinit_i = '1' then
s_counter <= (others => '0');
elsif counter_incr_i = '1' then
s_counter <= s_counter + 1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
counter_o <= s_counter;
counter_is_full_o <= '1' when s_counter = c_COUNTER_FULL else '0';
end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
sim/spec/testbench/nanoFIP_lib/wf_package.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_rx_deglitcher.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_rx_deserializer.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_rx_osc.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_tx_osc.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/nanoFIP_lib/wf_tx_serializer.vhd 0 → 100644
View file @ 3c5faced
This diff is collapsed.
sim/spec/testbench/tb_masterFIP.vhd
View file @ 3c5faced
This diff is collapsed.
syn/spec/spec_masterfip.xise
View file @ 3c5faced
This diff is collapsed.
syn/spec/tb_masterFIP.fdo 0 → 100644
View file @ 3c5faced
This diff is collapsed.
syn/spec_mt/spec_masterfip_mt.xise
View file @ 3c5faced
This diff is collapsed.
top/spec/spec_masterfip.vhd
View file @ 3c5faced
This diff is collapsed.
top/spec_mt/spec_masterfip_mt.ucf
View file @ 3c5faced
This diff is collapsed.
top/spec_mt/spec_masterfip_mt.vhd
View file @ 3c5faced
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment