onewire code cleanup; onewire at 100MHz

5ea0f26e · Evangelia Gousiou · 89953bc8 · 5ea0f26e · 5ea0f26e · 5ea0f26e
Commit 5ea0f26e authored Jul 29, 2016 by Evangelia Gousiou
7 changed files
--- a/rtl/fmc_masterFIP_core.vhd
+++ b/rtl/fmc_masterFIP_core.vhd
--- a/rtl/masterFIP_pkg.vhd
+++ b/rtl/masterFIP_pkg.vhd
@@ -395,11 +395,10 @@ package masterFIP_pkg is
     values_for_simul   : boolean := FALSE);
  port
    (clk_i              : in    std_logic;
-     clk_40m_i          : in    std_logic;   -- 40 MHz clock
     rst_i              : in    std_logic;
     speed_b0_i         : in    std_logic;
     speed_b1_i         : in    std_logic;
-     carrier_onewire_b  : inout std_logic;
+     onewire_b          : inout std_logic;
     fd_rxcdn_i         : in    std_logic;
     fd_rxd_i           : in    std_logic;
     fd_txer_i          : in    std_logic;
@@ -454,25 +453,24 @@ port
 end component;
-  component serialIdTempInt is
+  component onewire_interf is
  generic (
-    FREQ : integer := 40 --Frequency in MHz
+    freq : integer := 40 --Frequency in MHz
    );
  port(
-    Clk  : in std_logic;
+    clk_i  : in std_logic;
-    RstN : in std_logic;
+    rst_n_i: in std_logic;
-    SerialId : inout std_logic;                         -- IO to be connected to the chip (DS1822)
+    onewire_b : inout std_logic;                         -- IO to be connected to the chip (DS1822)
-    Id       : out   std_logic_vector(63 downto 0);     -- ID value
+    id_o       : out   std_logic_vector(63 downto 0);     -- ID value
-    Temp     : out   std_logic_vector(15 downto 0);     -- Temperature value (refreshed every second)
+    temper_o     : out   std_logic_vector(15 downto 0);     -- Temperature value (refreshed every second)
-    IdRead   : out   std_logic;                         -- ID value is valid
+    id_read_o   : out   std_logic;                         -- ID value is valid
-    Pps      : in    std_logic;                         -- Pulse per second (for temperature read)
+    pps_p_i      : in    std_logic;                         -- Pulse per second (for temperature read)
-    IdOk     : out   std_logic                          -- Same as IdRead, but not reset with RstN !!
+    id_ok_o     : out   std_logic                          -- Same as IdRead, but not reset with RstN !!
    );
 end component; 
 ---------------------------------------------------------------------------------------------------
  component carrier_info
    port

--- a/rtl/onewire_interf.vhd
+++ b/rtl/onewire_interf.vhd
--- a/rtl/serialIdTempInt.vhd
+++ b/rtl/serialIdTempInt.vhd
--- a/syn/spec/spec_masterfip.xise
+++ b/syn/spec/spec_masterfip.xise
--- a/syn/spec/tb_masterFIP.fdo
+++ b/syn/spec/tb_masterFIP.fdo
 ######################################################################
 ##
 ## Filename: tb_masterFIP.fdo
-## Created on: Fri Jul 22 18:19:57 W. Europe Daylight Time 2016
+## Created on: Fri Jul 22 18:44:57 W. Europe Daylight Time 2016
 ##
 ##  Auto generated by Project Navigator for Behavioral Simulation
 ##

--- a/top/spec/spec_masterfip.vhd
+++ b/top/spec/spec_masterfip.vhd
@@ -241,7 +241,7 @@ architecture rtl of spec_masterfip is
  signal led_clk_100m_aux               : std_logic_vector(7 downto 0);
  signal rx_err, rx_act, fd_txena       : std_logic;
-signal pllout_clk_40m, clk_40m : std_logic;
 --=================================================================================================
 --                                       architecture begin
 --=================================================================================================
@@ -279,7 +279,7 @@ begin
  port map
    (CLKFBOUT => pllout_clk_sys_fb,
     CLKOUT0  => pllout_clk_sys,
-     CLKOUT1  => pllout_clk_40m,
+     CLKOUT1  => open,
     CLKOUT2  => open,
     CLKOUT3  => open,
     CLKOUT4  => open,
@@ -294,11 +294,8 @@ begin
  port map
    (O => clk_100m_sys,
     I => pllout_clk_sys);
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  cmp_clk_40m_buf : BUFG
-  port map
-    (O => clk_40m,
-     I => pllout_clk_40m);
 ---------------------------------------------------------------------------------------------------
 --                                             RESET                                             --
@@ -432,13 +429,12 @@ begin
     values_for_simul   => FALSE)
  port map
    (clk_i              => clk_100m_sys,
-     clk_40m_i          => clk_40m,
     rst_i              => rst_sys,
     -- Bus speed
     speed_b0_i         => speed_b0_i,
     speed_b1_i         => speed_b1_i,
     -- One Wire
-     carrier_onewire_b  => carrier_onewire_b,
+     onewire_b          => carrier_onewire_b,
     -- FielDrive
     fd_rxcdn_i         => fd_rxcdn_i,
     fd_rxd_i           => fd_rxd_i,
@@ -510,26 +506,26 @@ begin
 --                                          SPEC 1-wire                                          --
 ---------------------------------------------------------------------------------------------------
-  cmp_carrier_onewire : xwb_onewire_master
+--  cmp_carrier_onewire : xwb_onewire_master
-  generic map
+--  generic map
-    (g_interface_mode      => CLASSIC,
+--    (g_interface_mode      => CLASSIC,
-     g_address_granularity => BYTE,
+--     g_address_granularity => BYTE,
-     g_num_ports           => 1,
+--     g_num_ports           => 1,
-     g_ow_btp_normal       => "5.0",
+--     g_ow_btp_normal       => "5.0",
-     g_ow_btp_overdrive    => "1.0")
+--     g_ow_btp_overdrive    => "1.0")
-  port map
+--  port map
-    (clk_sys_i             => clk_100m_sys,
+--    (clk_sys_i             => clk_100m_sys,
-     rst_n_i               => rst_sys_n,
+--     rst_n_i               => rst_sys_n,
-     slave_i               => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
+--     slave_i               => cnx_master_out(c_WB_SLAVE_SPEC_ONEWIRE),
-     slave_o               => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
+--     slave_o               => cnx_master_in(c_WB_SLAVE_SPEC_ONEWIRE),
-     desc_o                => open,
+--     desc_o                => open,
-     owr_pwren_o           => open,
+--     owr_pwren_o           => open,
-     owr_en_o              => carrier_owr_en,
+--     owr_en_o              => carrier_owr_en,
-     owr_i                 => carrier_owr_i);
+--     owr_i                 => carrier_owr_i);
+--
-  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
+--  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --  --
-  carrier_onewire_b       <= '0' when carrier_owr_en(0) = '1' else 'Z';
+--  carrier_onewire_b       <= '0' when carrier_owr_en(0) = '1' else 'Z';
-  carrier_owr_i(0)        <= carrier_onewire_b;
+--  carrier_owr_i(0)        <= carrier_onewire_b;
 ---------------------------------------------------------------------------------------------------