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Mock Turtle
Commit f72e4071 authored by Tristan Gingold's avatar Tristan Gingold
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Update mockturtle-debug.py

parent 266bf581
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Showing with 100 additions and 32 deletions
software/tools/mockturtle-debug.py
View file @ f72e4071
......@@ -29,7 +29,7 @@ HMQ_GCR_IRQ_COALESE = HMQ_GCR_BASE + 0x0c
CSR_APPID = CSR_BASE + 0x00
CSR_RESET = CSR_BASE + 0x04
CSR_ENABLE = CSR_BASE + 0x08
CSR_INT = CSR_BASE + 0x08
CSR_UADDR = CSR_BASE + 0x0c
CSR_CORESEL = CSR_BASE + 0x10
CSR_CORECNT = CSR_BASE + 0x14
......@@ -37,14 +37,20 @@ CSR_COREMEM = CSR_BASE + 0x18
CSR_UDATA = CSR_BASE + 0x1c
CSR_DBG_MSG = CSR_BASE + 0x20
CSR_DBG_POLL = CSR_BASE + 0x24
CSR_HMQ_SEL = CSR_BASE + 0x30
CSR_DBG_STATUS = CSR_BASE + 0x34
CSR_DBG_FORCE = CSR_BASE + 0x38
CSR_DBG_INSN_READY = CSR_BASE + 0x3c
CSR_DBG_CPU0_INSN = CSR_BASE + 0x40
CSR_DBG_CPU1_INSN = CSR_BASE + 0x44
CSR_DBG_MBX0 = CSR_BASE + 0x48
CSR_DBG_MBX1 = CSR_BASE + 0x4c
CSR_DBG_IMASK = CSR_BASE + 0x28
CSR_SMEM_OP = CSR_BASE + 0x2c
CSR_HMQI_STATUS_LO = CSR_BASE + 0x30
CSR_HMQI_STATUS_HI = CSR_BASE + 0x34
CSR_HMQO_STATUS_LO = CSR_BASE + 0x38
CSR_HMQO_STATUS_HI = CSR_BASE + 0x3c
CSR_HMQ_SEL = CSR_BASE + 0x40
CSR_DBG_STATUS = CSR_BASE + 0x44
CSR_DBG_FORCE = CSR_BASE + 0x48
CSR_DBG_INSN_READY = CSR_BASE + 0x4c
CSR_DBG_CPU0_INSN = CSR_BASE + 0x50
CSR_DBG_CPU1_INSN = CSR_BASE + 0x54
CSR_DBG_MBX0 = CSR_BASE + 0x58
CSR_DBG_MBX1 = CSR_BASE + 0x5c
def read_corenbr(csr):
return csr.readl(CSR_CORECNT)
......@@ -80,51 +86,112 @@ def disp_mq_slot(csr, base):
(status >> 1) & 1, status & 1))
def cmd_hmq(csr):
print ("CSR HMQI status: 0x{:08x} 0x{:08x}".format(
csr.readl(CSR_HMQI_STATUS_LO),
csr.readl(CSR_HMQI_STATUS_HI)))
print ("CSR HMQO status: 0x{:08x} 0x{:08x}".format(
csr.readl(CSR_HMQO_STATUS_LO),
csr.readl(CSR_HMQO_STATUS_HI)))
print ("HMQ GCR:")
count = csr.readl(HMQ_GCR_COUNT)
nbr_in_slots = count & 0xff
nbr_out_slots = (count >> 8) & 0xff
print (" COUNT: 0x{:08x} IN: {}, OUT: {}".format(
count, nbr_in_slots, nbr_out_slots))
nbr_slots = count & 0xff
print (" COUNT: 0x{:08x}".format(count))
status = csr.readl(HMQ_GCR_STATUS)
print (" STATUS: 0x{:08x} IN: 0x{:04x}, OUT: 0x{:04x}".format(
print (" STATUS: 0x{:08x} IN: 0x{:02x}, OUT: 0x{:02x}".format(
status, (status >> 16) & 0xffff, status & 0xffff))
print (" IRQ MASK: 0x{:08x}".format(csr.readl(HMQ_GCR_IRQ_MASK)))
print (" IRQ COALESE: 0x{:08x}".format(csr.readl(HMQ_GCR_IRQ_COALESE)))
for i in range(nbr_in_slots):
base = HMQ_IN_BASE + (i << 10)
for i in range(nbr_slots):
csr.writel(CSR_HMQ_SEL, i)
print ("HMQ IN#{}:".format(i))
disp_mq_slot(csr, base)
for i in range(nbr_out_slots):
base = HMQ_OUT_BASE + (i << 10)
disp_mq_slot(csr, HMQ_IN_BASE)
print ("HMQ OUT#{}:".format(i))
disp_mq_slot(csr, base)
disp_mq_slot(csr, HMQ_OUT_BASE)
def cmd_whmq(csr):
count = csr.readl(HMQ_GCR_COUNT)
nbr_in_slots = count & 0xff
nbr_slots = count & 0xff
status = csr.readl(HMQ_GCR_STATUS)
out_status = status & 0xffff
in_status = (status >> 16) & 0xffff
for i in range(nbr_in_slots):
if ((in_status >> i) & 1) != 1:
print ("HMQ IN#{} is busy".format(i))
in_status = status & 0xffff
out_status = (status >> 16) & 0xffff
for i in range(nbr_slots):
if ((out_status >> i) & 1) != 1:
print ("HMQ OUT#{} is busy".format(i))
continue
base = HMQ_IN_BASE + (i << 10)
print ("Write to HMQ#{}".format(i))
base = HMQ_OUT_BASE
csr.writel(CSR_HMQ_SEL, i)
# Claim
csr.writel(base + 0, 1 << 24)
# Write
csr.writel(base + 8, 0x12345678)
csr.writel(base + 12, 0xabcd0000 + i)
# Header
csr.writel(base + 0x1000, 2)
# Data
csr.writel(base + 0x2000, 0x0abcd000 + i)
csr.writel(base + 0x2004, 0x00abcd00)
csr.writel(base + 0x2008, 0x000abcd0)
csr.writel(base + 0x200c, 0x0000abcd)
# Ready
csr.writel(base + 0, 1 << 26)
def cmd_rhmq(csr):
count = csr.readl(HMQ_GCR_COUNT)
nbr_slots = count & 0xff
status = csr.readl(HMQ_GCR_STATUS)
in_status = status & 0xffff
for i in range(nbr_slots):
if ((in_status >> i) & 1) != 1:
continue
print ("Read from HMQ#{}".format(i))
base = HMQ_IN_BASE
csr.writel(CSR_HMQ_SEL, i)
for j in range(4):
print (" H[{}]: 0x{:08x}".format(
j, csr.readl(base + 0x1000 + 4*j)))
for j in range(8):
print (" D[{}]: 0x{:08x}".format(
j, csr.readl(base + 0x2000 + 4*j)))
# Discard
csr.writel(base + 0, 1 << 27)
def read_crom(csr, off):
return csr.readl(CROM_BASE + 4 * off)
def disp_mq(csr, offset):
sizes = read_crom(csr, offset)
ep_id = read_crom(csr, offset + 1)
p2entries = (sizes >> 16) & 0xff
p2width = (sizes >> 8) & 0xff
p2header = (sizes >> 0) & 0xff
return "entries:2^{} width:2^{} header:2^{} endpoint:{:08x}".format(
p2entries, p2width, p2header, ep_id)
def cmd_crom(csr):
print ("CROM:")
for i in range(64):
print ("{:04x}: {:08x}".format(i * 4, csr.readl(CROM_BASE + 4 * i)))
print ("Signature: {:08x}".format(read_crom(csr, 0)))
print ("MT revision: {:08x}".format(read_crom(csr, 1)))
print ("Clock freq: {}".format(read_crom(csr, 3)))
print ("config: {:08x}".format(read_crom(csr, 4)))
print ("APP Id: {:08x}".format(read_crom(csr, 5)))
ncpus = read_crom(csr, 6)
print ("CPU count: {:08x}".format(ncpus))
print ("Shared RAM: {:08x}".format(read_crom(csr, 7)))
for i in range(ncpus):
print ("CPU#{}:".format(i))
print (" memsize: {:08x}".format(read_crom(csr, 8+i)))
nhmq = read_crom(csr, 16+i)
print (" hmq slots: {}".format(nhmq))
nrmq = read_crom(csr, 24+i)
print (" rmq slots: {}".format(nrmq))
for j in range(nhmq):
print (" hmq#{}: {}".format(
j, disp_mq(csr, 128 + 16 * i + 2 * j)))
for j in range(nrmq):
print (" rmq#{}: {}".format(
j, disp_mq(csr, 256 + 16 * i + 2 * j)))
class CpuPort(object):
def __init__(self, csr, cpu):
......@@ -661,6 +728,7 @@ def main():
'mbx': cmd_mbx,
'hmq': cmd_hmq,
'whmq': cmd_whmq,
'rhmq': cmd_rhmq,
'crom': cmd_crom,
'term': cmd_term,
'reset': cmd_reset,
......
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