..same as before:-s

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@125 7f0067c9-7624-46c7-bd39-3fb5400c0213

..same as before:-s
git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@125 7f0067c9-7624-46c7-bd39-3fb5400c0213
7e6a0c2a · egousiou · 7da7370b · 7e6a0c2a · 7e6a0c2a · 7e6a0c2a
Commit 7e6a0c2a authored Jan 21, 2011 by egousiou
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Showing with 17 additions and 18 deletions

DualClkRAM.vhd DualClkRAM.vhd +13 -13

wf_crc.vhd wf_crc.vhd +0 -1

wf_rx_deserializer.vhd wf_rx_deserializer.vhd +4 -4

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--- a/DualClkRAM.vhd
+++ b/DualClkRAM.vhd
@@ -32,8 +32,8 @@ use PROASIC3.all;
 --
 --
 --! @brief     Instantiation of a template RAM4K9 memory component with
--!            word width : 8 bits and 
+--!              o word width : 8 bits and 
--!            depth      : 512 bytes.
+--!              o depth      : 512 bytes.
 -- 
 -- 
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
@@ -76,13 +76,13 @@ use PROASIC3.all;
 entity DualClkRAM is 
  port(
  -- INPUTS 
-    -- Inpouts concerning port A 
+    -- Inputs concerning port A 
    CLKA   : in std_logic;                     --! clock A for synchronous read/ write operations
    ADDRA  : in std_logic_vector (8 downto 0); --! address A
    DINA   : in std_logic_vector (7 downto 0); --! data in A
    RWA    : in std_logic;                     --! read/ write mode; 1 for reading, 0 for writing 
-    -- Inpouts concerning port B
+    -- Inputs concerning port B
    CLKB   : in std_logic;                     --! clock B for synchronous read/ write operations
    ADDRB  : in std_logic_vector (8 downto 0); --! address B
    DINB   : in std_logic_vector (7 downto 0); --! data in B
@@ -116,14 +116,14 @@ architecture RAM4K9 of  DualClkRAM is
 --! is possible.
 --! WIDTHA0, WIDTHA1 and WIDTHB0, WIDTHB1 :
--! Apect ratio configuration.
+--! Aspect ratio configuration.
 --! WENA, WENB :
 --! Switching between Read and Write modes for the respective ports.
 --! A Low indicates Write operation and a High indicates a Read.
 --! BLKA, BLKB : 
--! Activw low enable for the respective ports.
+--! Active low enable for the respective ports.
 --! PIPEA, PIPEB :
 --! Control of the optional pipeline stages.
@@ -189,19 +189,19 @@ begin
 ---------------------------------------------------------------------------------------------------  
 --!@brief: Instantiation of the component RAM4K9.
 --! The following configuration has been applied: 
--! aspect ratio   : 9 x 512   (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1                 : VCC)
+--!  o aspect ratio   : 9 x 512  (WIDTHA0, WIDTHA1, WIDTHB0, WIDTHB1                 : VCC)
--! word width     : 8 bits    (DINA8, DINB8: GND, DOUTA8, DOUTB8                  : open)
+--!  o word width     : 8 bits   (DINA8, DINB8: GND, DOUTA8, DOUTB8                  : open)
--! memory depth   : 512 bytes (ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
+--!  o memory depth   : 512 bytes(ADDRA11, ADDRA10, ADDRA9, ADDRB11, ADDRB10, ADDRB9 : GND)
--! BLKA, BLKB     : GND
+--!  o BLKA, BLKB     : GND      (ports enabled)
--! PIPEA, PIPEB   : GND       (not pipelined read)
+--!  o PIPEA, PIPEB   : GND      (not pipelined read)
--! WMODEA, WMODEB : GND       (in write mode the output retains the data from the previous read)
+--!  o WMODEA, WMODEB : GND      (in write mode the output retains the data from the previous read)
    A9D8DualClkRAM_R0C0 : RAM4K9
    port map(
    -- INPUTS 
      -- INPUTS concerning port A
-      -- datain A (1 byte, (7 downto 0))    
+      -- data in A (1 byte, (7 downto 0))    
      DINA8   => GROUND,
      DINA7   => DINA(7),
      DINA6   => DINA(6),

--- a/wf_crc.vhd
+++ b/wf_crc.vhd
@@ -33,7 +33,6 @@ use work.WF_PACKAGE.all;     --! definitions of types, constants, entities
 --
 --
 --! @author    Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)\n
--!            Evangelia Gousiou     (Evangelia.Gousiou@cern.ch)    \n
 --
 --
 --! @date      08/2010

--- a/wf_rx_deserializer.vhd
+++ b/wf_rx_deserializer.vhd
@@ -200,8 +200,8 @@ architecture rtl of WF_rx_deserializer is
  signal s_manch_r_edge_p, s_manch_f_edge_p                       : std_logic;
  signal s_manch_bit_index, s_manch_bit_index_top                 : unsigned(3 downto 0);
  signal s_byte                                                   : std_logic_vector (7 downto 0);
-  signal s_CRC_ok_p_buff, s_arriving_fes                          : std_logic_vector (15 downto 0);
+  signal s_arriving_fes                                          : std_logic_vector (15 downto 0);
-  signal s_arriving_fes                                           : std_logic_vector (14 downto 0);
+  signal s_CRC_ok_p_buff                                          : std_logic_vector (14 downto 0);
 --=================================================================================================
 --                                      architecture begin
@@ -563,7 +563,7 @@ architecture rtl of WF_rx_deserializer is
      end if;
    end process;
  --  --  --  --  --  --  --  --  --  --  -- 
-  s_fes_detected_p <= '1' when s_arriving_fes = (c_FES);
+  s_fes_detected_p <= '1' when s_arriving_fes = (c_FES) and  s_receiving_bytes = '1' else '0';
 ---------------------------------------------------------------------------------------------------
@@ -650,7 +650,7 @@ architecture rtl of WF_rx_deserializer is
            if s_sample_manch_bit_p_d1 = '1' then          -- each manch. bit arrival. In total 15
                                                           -- delays have to be added in order to 
                                                           -- arrive to the FES.
-              s_CRC_ok_p_buff     <= s_CRC_ok_p_buff(14 downto 0) & s_CRC_ok_p;
+              s_CRC_ok_p_buff     <= s_CRC_ok_p_buff(13 downto 0) & s_CRC_ok_p;
            end if;
          end if;