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nanoFIP - Gateware
Commit a702526a authored by egousiou's avatar egousiou
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changes for slone mode 

(consumed vars: PDU_TYPE and Length bytes received, 
produced vars: VAR3_ACC enabled only if ctrl, PDU_TYPE, Length and CRC bytes are correct;
sampling of dat_i takes place on the 1st clk tick after VAR3_ACC deasserted)

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@73 7f0067c9-7624-46c7-bd39-3fb5400c0213
parent 4303602e
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DualClkRAM.vhd
View file @ a702526a
...@@ -71,14 +71,14 @@ entity DualClkRAM is ...@@ -71,14 +71,14 @@ entity DualClkRAM is
port( port(
-- INPUTS -- INPUTS
-- Inpouts concerning port A -- Inpouts concerning port A
DINA : in std_logic_vector(7 downto 0); --! data in A DINA : in std_logic_vector (7 downto 0); --! data in A
ADDRA : in std_logic_vector(8 downto 0); --! address A ADDRA : in std_logic_vector (8 downto 0); --! address A
RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWA : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKA : in std_logic; --! clock A for synchronous read/ write operations CLKA : in std_logic; --! clock A for synchronous read/ write operations
-- may be indipendant of clock B -- may be indipendant of clock B
-- Inpouts concerning port B -- Inpouts concerning port B
DINB : in std_logic_vector(7 downto 0); --! data in B DINB : in std_logic_vector (7 downto 0); --! data in B
ADDRB : in std_logic_vector(8 downto 0); --! address B ADDRB : in std_logic_vector (8 downto 0); --! address B
RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing RWB : in std_logic; --! read/ write mode; 1 for reading, 0 for writing
CLKB : in std_logic; --! clock B for synchronous read/ write operations CLKB : in std_logic; --! clock B for synchronous read/ write operations
-- may be indipendant of clock A -- may be indipendant of clock A
...@@ -87,10 +87,10 @@ entity DualClkRAM is ...@@ -87,10 +87,10 @@ entity DualClkRAM is
-- OUTPUTS -- OUTPUTS
-- Output concerning port A -- Output concerning port A
DOUTA : out std_logic_vector(7 downto 0); --! data out A DOUTA : out std_logic_vector (7 downto 0); --! data out A
-- Output concerning port B -- Output concerning port B
DOUTB : out std_logic_vector(7 downto 0) --! data out B DOUTB : out std_logic_vector (7 downto 0) --! data out B
); );
end DualClkRAM; end DualClkRAM;
......
nanofip.vhd
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dpblockram_clka_rd_clkb_wr_syn.vhd → wf_DualClkRAM_clka_rd_clkb_wr.vhd
View file @ a702526a
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @file dpblockram_clka_rd_clkb_wr_syn.vhd --! @file wf_DualClkRAM_clka_rd_clkb_wr.vhd
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- Standard library -- Standard library
...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -11,7 +11,7 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- dpblockram_clka_rd_clkb_wr_syn -- -- wf_DualClkRAM_clka_rd_clkb_wr --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -58,59 +58,59 @@ use IEEE.NUMERIC_STD.all; -- conversion functions ...@@ -58,59 +58,59 @@ use IEEE.NUMERIC_STD.all; -- conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for dpblockram_clka_rd_clkb_wr_syn --! Entity declaration for wf_DualClkRAM_clka_rd_clkb_wr
--================================================================================================= --=================================================================================================
entity dpblockram_clka_rd_clkb_wr is entity wf_DualClkRAM_clka_rd_clkb_wr is
generic (c_data_length : integer := 8; -- 8: length of data word (1 byte) generic (c_data_length : integer := 8; -- 8: length of data word (1 byte)
c_addr_length : integer := 9); -- 2^9: memory depth (512 bytes) c_addr_length : integer := 9); -- 2^9: memory depth (512 bytes)
port ( port (
clk_A_i : in std_logic; clk_A_i : in std_logic;
addr_A_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_A_i : in std_logic_vector (c_addr_length - 1 downto 0);
clk_B_i : in std_logic; clk_B_i : in std_logic;
addr_B_i : in std_logic_vector(c_addr_length - 1 downto 0); addr_B_i : in std_logic_vector (c_addr_length - 1 downto 0);
data_B_i : in std_logic_vector(c_data_length - 1 downto 0); data_B_i : in std_logic_vector (c_data_length - 1 downto 0);
write_en_B_i : in std_logic; write_en_B_i : in std_logic;
data_A_o : out std_logic_vector(c_data_length -1 downto 0) data_A_o : out std_logic_vector (c_data_length -1 downto 0)
); );
end dpblockram_clka_rd_clkb_wr; end wf_DualClkRAM_clka_rd_clkb_wr;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture syn of dpblockram_clka_rd_clkb_wr is architecture syn of wf_DualClkRAM_clka_rd_clkb_wr is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: component DualClkRam declaration --!@brief: component DualClkRam declaration
component DualClkRam is component DualClkRam is
port( port(
DINA : in std_logic_vector(7 downto 0); DINA : in std_logic_vector (7 downto 0);
ADDRA : in std_logic_vector(8 downto 0); ADDRA : in std_logic_vector (8 downto 0);
RWA : in std_logic; RWA : in std_logic;
CLKA : in std_logic; CLKA : in std_logic;
DINB : in std_logic_vector(7 downto 0); DINB : in std_logic_vector (7 downto 0);
ADDRB : in std_logic_vector(8 downto 0); ADDRB : in std_logic_vector (8 downto 0);
RWB : in std_logic; RWB : in std_logic;
CLKB : in std_logic; CLKB : in std_logic;
RESETn : in std_logic; RESETn : in std_logic;
DOUTA : out std_logic_vector(7 downto 0); DOUTA : out std_logic_vector (7 downto 0);
DOUTB : out std_logic_vector(7 downto 0) DOUTB : out std_logic_vector (7 downto 0)
); );
end component DualClkRam; end component DualClkRam;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
type t_data_o_A_array is array (natural range <>) of std_logic_vector(7 downto 0); type t_data_o_A_array is array (natural range <>) of std_logic_vector (7 downto 0);
signal data_o_A_array : t_data_o_A_array(0 to 2); -- keeps the DOUTA of each one of the memories signal data_o_A_array : t_data_o_A_array (0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic; signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector(7 downto 0); signal s_zeros : std_logic_vector (7 downto 0);
--================================================================================================= --=================================================================================================
...@@ -126,7 +126,7 @@ s_rwB <= not write_en_B_i; ...@@ -126,7 +126,7 @@ s_rwB <= not write_en_B_i;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: memory triplication --!@brief: memory triplication
--! The component DualClkRam is generated three times. --! The component DualClkRam is generated three times.
--! Port A is used for reading, port B for writing. --! Port A is used for reading only, port B for writing only.
--! The input DINB is written in the same position in the 3 memories. --! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array data_o_A_array. --! The output DOUTA from each memory is kept in the array data_o_A_array.
......
wf_consumed_vars.vhd
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wf_crc.vhd
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...@@ -75,7 +75,7 @@ port ( ...@@ -75,7 +75,7 @@ port (
-- OUTPUTS -- OUTPUTS
crc_ok_p : out std_logic; --! signaling of a correct received crc syndrome crc_ok_p : out std_logic; --! signaling of a correct received crc syndrome
crc_o : out std_logic_vector(c_GENERATOR_POLY_length-1 downto 0)--!calculated crc crc_o : out std_logic_vector (c_GENERATOR_POLY_length-1 downto 0)--!calculated crc
-- 2 bytes -- 2 bytes
); );
...@@ -92,11 +92,11 @@ architecture rtl of wf_crc is ...@@ -92,11 +92,11 @@ architecture rtl of wf_crc is
constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) := constant c_GENERATOR_POLY: std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0) :=
"0001110111001111"; "0001110111001111";
--! crc check mask --! crc check mask
constant c_VERIFICATION_MASK:std_logic_vector(c_GENERATOR_POLY_length-1 downto 0) := constant c_VERIFICATION_MASK:std_logic_vector (c_GENERATOR_POLY_length-1 downto 0) :=
"0001110001101011"; "0001110001101011";
signal s_crc_bit_ready_p : std_logic; signal s_crc_bit_ready_p : std_logic;
signal s_q, s_q_nx, s_q_check_mask : std_logic_vector(c_GENERATOR_POLY_length - 1 downto 0); signal s_q, s_q_nx, s_q_check_mask : std_logic_vector (c_GENERATOR_POLY_length - 1 downto 0);
--================================================================================================= --=================================================================================================
-- architecture begin -- architecture begin
...@@ -152,8 +152,11 @@ crc_o <= not s_q; ...@@ -152,8 +152,11 @@ crc_o <= not s_q;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief Combinatorial process Syndrome_Verification: For the verification of a received crc --!@brief Combinatorial process Syndrome_Verification: On the reception, the crc is being
--! syndrome, the outputs of the 16 flip-flops are compared to the predefined mask --! calculated as data is arriving (same as in the transmission) and it is being compared to the
--! predefined c_VERIFICATION_MASK. When the crc calculated from the received data maches the
--! c_VERIFICATION_MASK, it means a correct crc word has been received and the signal crc_ok_p
--! gives a pulse.
Syndrome_Verification: process(s_q, s_crc_bit_ready_p) Syndrome_Verification: process(s_q, s_crc_bit_ready_p)
......
wf_engine_control.vhd
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wf_dec_m_ids.vhd → wf_model_constr_decoder.vhd
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--=========================================================================== --===========================================================================
--! @file wf_dec_m_ids.vhd --! @file wf_model_constr_decoder.vhd
--=========================================================================== --===========================================================================
--! standard library --! standard library
...@@ -14,13 +14,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -14,13 +14,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_dec_m_ids -- -- wf_model_constr_decoder --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_dec_m_ids -- unit name wf_model_constr_decoder
-- --
-- --
--! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID --! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID
...@@ -61,9 +61,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -61,9 +61,9 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_dec_m_ids --! Entity declaration for wf_model_constr_decoder
--================================================================================================= --=================================================================================================
entity wf_dec_m_ids is entity wf_model_constr_decoder is
port ( port (
-- INPUTS -- INPUTS
...@@ -80,14 +80,14 @@ entity wf_dec_m_ids is ...@@ -80,14 +80,14 @@ entity wf_dec_m_ids is
-- OUTPUTS -- OUTPUTS
-- WorldFIP settings nanoFIP output -- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector(1 downto 0); --! Identification selection s_id_o : out std_logic_vector (1 downto 0); --! Identification selection
-- Output to wf_produced_vars -- Output to wf_produced_vars
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
); );
end entity wf_dec_m_ids; end entity wf_model_constr_decoder;
...@@ -95,13 +95,13 @@ end entity wf_dec_m_ids; ...@@ -95,13 +95,13 @@ end entity wf_dec_m_ids;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_dec_m_ids is architecture rtl of wf_model_constr_decoder is
signal s_load_val : std_logic; signal s_load_val : std_logic;
signal s_c, s_c_n : unsigned(8 downto 0); signal s_c, s_c_n : unsigned(8 downto 0);
signal s_m_even, s_m_odd : std_logic_vector(3 downto 0); signal s_m_even, s_m_odd : std_logic_vector (3 downto 0);
signal s_c_even, s_c_odd : std_logic_vector(3 downto 0); signal s_c_even, s_c_odd : std_logic_vector (3 downto 0);
--================================================================================================= --=================================================================================================
...@@ -148,7 +148,7 @@ begin ...@@ -148,7 +148,7 @@ begin
end if; end if;
end process; end process;
s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c s_id_o <= std_logic_vector (s_c((s_c'left - 1) downto (s_c'left - 2))); -- 2 msb of s_c
end architecture rtl; end architecture rtl;
......
wf_package.vhd
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wf_produced_vars.vhd
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reset_logic.vhd → wf_reset_unit.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file reset_logic.vhd --! @file wf_reset_unit.vhd
--================================================================================================= --=================================================================================================
--! standard library --! standard library
...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -15,13 +15,13 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_reset_logic -- -- wf_reset_unit --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name: reset_logic -- unit name: wf_reset_unit
-- --
--! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset --! @brief Reset logic. Manages the three nanoFIP reset signals: internal reset, FIELDRIVE reset
--! and user interface reset (RSTON) --! and user interface reset (RSTON)
...@@ -64,9 +64,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -64,9 +64,9 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--================================================================================================= --=================================================================================================
--! Entity declaration for reset_logic --! Entity declaration for wf_reset_unit
--================================================================================================= --=================================================================================================
entity reset_logic is entity wf_reset_unit is
generic (c_rstin_c_length : integer := 4); --! rstin counter length generic (c_rstin_c_length : integer := 4); --! rstin counter length
port ( port (
...@@ -92,16 +92,16 @@ entity reset_logic is ...@@ -92,16 +92,16 @@ entity reset_logic is
-- nanoFIP output to FIELDRIVE -- nanoFIP output to FIELDRIVE
fd_rstn_o : out std_logic --! FIELDRIVE reset, active low fd_rstn_o : out std_logic --! FIELDRIVE reset, active low
); );
end entity reset_logic; end entity wf_reset_unit;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of reset_logic is architecture rtl of wf_reset_unit is
signal s_rst : std_logic; signal s_rst : std_logic;
signal s_rstin_buff : std_logic_vector(2 downto 0); signal s_rstin_buff : std_logic_vector (2 downto 0);
signal s_rstin_c : unsigned(4 downto 0) := (others=>'0'); -- counter init for simulation purpuses signal s_rstin_c : unsigned(4 downto 0) := (others=>'0'); -- counter init for simulation purpuses
......
wf_rx.vhd
View file @ a702526a
...@@ -75,8 +75,11 @@ entity wf_rx is ...@@ -75,8 +75,11 @@ entity wf_rx is
-- User interface general signal -- User interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signal from the wf_engine_control
reset_rx_unit_p_i : in std_logic;
-- signals from the wf_rx_tx_osc -- signals from the wf_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
...@@ -95,10 +98,9 @@ entity wf_rx is ...@@ -95,10 +98,9 @@ entity wf_rx is
-- OUTPUTS -- OUTPUTS
-- needed by the wf_consumed and wf_engine_control -- needed by the wf_consumed and wf_engine_control
byte_ready_p_o : out std_logic; --! indication of a valid data byte byte_ready_p_o : out std_logic; --! indication of a valid data byte
byte_o : out std_logic_vector(7 downto 0) ; --! retreived data byte byte_o : out std_logic_vector (7 downto 0) ; --! retreived data byte
-- needed by the wf_engine_control -- needed by the wf_engine_control
crc_ok_p_o : out std_logic; crc_ok_p_o : out std_logic;
...@@ -106,7 +108,7 @@ entity wf_rx is ...@@ -106,7 +108,7 @@ entity wf_rx is
fss_decoded_p_o : out std_logic; fss_decoded_p_o : out std_logic;
last_byte_p_o : out std_logic; last_byte_p_o : out std_logic;
-- needed by the status_gen -- needed by the wf_status_bytes_gen
code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation code_violation_p_o : out std_logic; --! indicator of a manchester 2 code violation
-- needed by the wf_rx_tx_osc -- needed by the wf_rx_tx_osc
...@@ -139,14 +141,14 @@ architecture rtl of wf_rx is ...@@ -139,14 +141,14 @@ architecture rtl of wf_rx is
signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic; signal s_frame_start_wrong_bit, s_frame_start_last_bit : std_logic;
signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic; signal s_frame_end_detected_p, s_frame_end_detection, s_frame_end_wrong_bit : std_logic;
signal s_violation_check, s_code_violation_p : std_logic; signal s_check_violation, s_code_violation_p : std_logic;
signal s_calculate_crc, s_crc_ok_p, s_crc_ok, s_start_crc_p : std_logic; signal s_calculate_crc, s_crc_ok_p, s_crc_ok, s_start_crc_p : std_logic;
signal s_byte_ok, s_write_bit_to_byte, s_rx_data_filtered_d: std_logic; signal s_byte_ok, s_write_bit_to_byte, s_rx_data_filtered_d: std_logic;
signal s_byte : std_logic_vector(7 downto 0); signal s_byte : std_logic_vector (7 downto 0);
signal s_rx_data_filtered_buff : std_logic_vector(1 downto 0); signal s_rx_data_filtered_buff : std_logic_vector (1 downto 0);
...@@ -158,16 +160,15 @@ architecture rtl of wf_rx is ...@@ -158,16 +160,15 @@ architecture rtl of wf_rx is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief instantiation of the crc calculator unit --!@brief instantiation of the crc calculator unit
crc_verification : wf_crc crc_verification : wf_crc
generic map( generic map(c_GENERATOR_POLY_length => 16)
c_GENERATOR_POLY_length => 16)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
start_crc_p_i => s_start_crc_p, start_crc_p_i => s_start_crc_p,
data_bit_ready_p_i => s_write_bit_to_byte, data_bit_ready_p_i => s_write_bit_to_byte,
data_bit_i => rx_data_filtered_i, data_bit_i => rx_data_filtered_i,
crc_o => open, crc_o => open,
crc_ok_p => s_crc_ok_p crc_ok_p => s_crc_ok_p
); );
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -204,7 +205,8 @@ architecture rtl of wf_rx is ...@@ -204,7 +205,8 @@ architecture rtl of wf_rx is
s_frame_start_wrong_bit, s_manch_f_edge, rx_st, s_frame_start_wrong_bit, s_manch_f_edge, rx_st,
s_frame_end_detected_p, s_frame_end_wrong_bit, s_frame_end_detected_p, s_frame_end_wrong_bit,
rx_data_f_edge_i, s_edge_outside_manch_window, rx_data_f_edge_i, s_edge_outside_manch_window,
s_code_violation_p,s_bit_r_edge, s_manch_r_edge ) s_code_violation_p,s_bit_r_edge, s_manch_r_edge,
reset_rx_unit_p_i )
begin begin
nx_rx_st <= idle; nx_rx_st <= idle;
...@@ -255,7 +257,7 @@ architecture rtl of wf_rx is ...@@ -255,7 +257,7 @@ architecture rtl of wf_rx is
end if; end if;
-- A small delay is expected between the rx_data_i and the rx_data_filtered_i (output of the -- A small delay is expected between the rx_data_i and the rx_data_filtered_i (output of the
-- deglitcher) which means that the last falling edge of the preamble of rx_data_i arrives -- wf_rx_deglitcher) which means that the last falling edge of the preamble of rx_data_i arrives
-- earlier than the one of the rx_data_filtered_i. the state switch_to _deglitched is used for -- earlier than the one of the rx_data_filtered_i. the state switch_to _deglitched is used for
-- this purpose. -- this purpose.
...@@ -284,7 +286,7 @@ architecture rtl of wf_rx is ...@@ -284,7 +286,7 @@ architecture rtl of wf_rx is
when data_field_byte => when data_field_byte =>
if s_frame_end_detected_p = '1' then if s_frame_end_detected_p = '1' or reset_rx_unit_p_i = '1' then
nx_rx_st <= idle; nx_rx_st <= idle;
-- Is there a code violation that does not correspond to the queue pattern? -- Is there a code violation that does not correspond to the queue pattern?
elsif s_frame_end_wrong_bit = '1' and s_code_violation_p = '1' then elsif s_frame_end_wrong_bit = '1' and s_code_violation_p = '1' then
...@@ -362,7 +364,7 @@ architecture rtl of wf_rx is ...@@ -362,7 +364,7 @@ architecture rtl of wf_rx is
s_start_pointer <= to_unsigned(0,s_start_pointer'length); s_start_pointer <= to_unsigned(0,s_start_pointer'length);
s_load_pointer <= '0'; s_load_pointer <= '0';
s_decr_pointer <= '0'; s_decr_pointer <= '0';
s_frame_start_bit <='0'; s_frame_start_bit <= '0';
fss_decoded_p_o <= '0'; fss_decoded_p_o <= '0';
s_write_bit_to_byte <= '0'; s_write_bit_to_byte <= '0';
s_byte_ok <= '0'; s_byte_ok <= '0';
...@@ -413,7 +415,7 @@ architecture rtl of wf_rx is ...@@ -413,7 +415,7 @@ architecture rtl of wf_rx is
s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and s_byte_ok <= s_pointer_is_zero and sample_manch_bit_p_i and
(not s_frame_end_detected_p); (not s_frame_end_detected_p);
s_queue_bit <= FRAME_END(to_integer(resize(pointer,4))); s_queue_bit <= FRAME_END(to_integer(resize(pointer,4)));
code_violation_p_o <= s_code_violation_p; code_violation_p_o <= s_code_violation_p and s_frame_end_wrong_bit;
s_start_crc_p <= '0'; s_start_crc_p <= '0';
s_calculate_crc <= '1'; s_calculate_crc <= '1';
s_frame_start_bit <= '0'; s_frame_start_bit <= '0';
...@@ -448,7 +450,7 @@ architecture rtl of wf_rx is ...@@ -448,7 +450,7 @@ architecture rtl of wf_rx is
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- extra concurrent signal assignments -- extra concurrent signal assignments
s_code_violation_p <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_violation_check; s_code_violation_p <= (not (rx_data_filtered_i xor s_rx_data_filtered_d)) and s_check_violation;
s_pointer_is_zero <= '1' when pointer = 0 else '0'; s_pointer_is_zero <= '1' when pointer = 0 else '0';
-- s_frame_start_last_bit <= s_pointer_is_zero and s_frame_start_correct_bit and sample_manch_bit_p_i; -- s_frame_start_last_bit <= s_pointer_is_zero and s_frame_start_correct_bit and sample_manch_bit_p_i;
...@@ -565,14 +567,14 @@ end process; ...@@ -565,14 +567,14 @@ end process;
-- 0 V- 1 -- 0 V- 1
-- rx_data_filtered_i: __|--|____|--|__ -- rx_data_filtered_i: __|--|____|--|__
-- s_rx_data_filtered_d: __|--|____|--|__ -- s_rx_data_filtered_d: __|--|____|--|__
-- s_violation_check: ^ ^ ^ -- s_check_violation: ^ ^ ^
Check_code_violations: process(uclk_i) Check_code_violations: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if nFIP_rst_i = '1' then if nFIP_rst_i = '1' then
byte_ready_p_o <='0'; byte_ready_p_o <='0';
s_violation_check <='0'; s_check_violation <='0';
s_sample_bit_p_d1 <='0'; s_sample_bit_p_d1 <='0';
s_sample_bit_p_d2 <='0'; s_sample_bit_p_d2 <='0';
s_rx_data_filtered_d <='0'; s_rx_data_filtered_d <='0';
...@@ -581,7 +583,7 @@ end process; ...@@ -581,7 +583,7 @@ end process;
if sample_manch_bit_p_i = '1' then if sample_manch_bit_p_i = '1' then
s_rx_data_filtered_d <= rx_data_filtered_i; s_rx_data_filtered_d <= rx_data_filtered_i;
end if; end if;
s_violation_check <= s_sample_bit_p_d2; s_check_violation <= s_sample_bit_p_d2;
s_sample_bit_p_d2 <= s_sample_bit_p_d1; s_sample_bit_p_d2 <= s_sample_bit_p_d1;
s_sample_bit_p_d1 <= sample_bit_p_i; s_sample_bit_p_d1 <= sample_bit_p_i;
byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p); byte_ready_p_o <= s_byte_ok and (not s_frame_end_detected_p);
......
deglitcher.vhd → wf_rx_deglitcher.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file deglitcher.vhd --! @file wf_rx_deglitcher.vhd
--================================================================================================= --=================================================================================================
--! Standard library --! Standard library
...@@ -12,7 +12,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,7 +12,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- deglitcher -- -- wf_rx_deglitcher --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
...@@ -37,7 +37,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -37,7 +37,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
-- --
--! \n<b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_osc \n --! wf_osc \n
--! reset_logic \n --! wf_reset_unit \n
-- --
-- --
--! \n<b>Modified by:</b>\n --! \n<b>Modified by:</b>\n
...@@ -62,7 +62,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -62,7 +62,7 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--! Entity declaration for wf_deglitcher --! Entity declaration for wf_deglitcher
--================================================================================================= --=================================================================================================
entity deglitcher is entity wf_rx_deglitcher is
generic (C_ACULENGTH : integer := 10); generic (C_ACULENGTH : integer := 10);
port( port(
...@@ -70,7 +70,7 @@ entity deglitcher is ...@@ -70,7 +70,7 @@ entity deglitcher is
-- User interface general signal -- User interface general signal
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- FIELDRIVE input signal -- FIELDRIVE input signal
...@@ -86,14 +86,14 @@ entity deglitcher is ...@@ -86,14 +86,14 @@ entity deglitcher is
rx_data_filtered_o : out std_logic; rx_data_filtered_o : out std_logic;
sample_manch_bit_p_o : out std_logic sample_manch_bit_p_o : out std_logic
); );
end deglitcher; end wf_rx_deglitcher;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture Behavioral of deglitcher is architecture Behavioral of wf_rx_deglitcher is
signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0); signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rx_data_filtered: STD_LOGIC; signal s_rx_data_filtered: STD_LOGIC;
...@@ -115,7 +115,7 @@ process(uclk_i) ...@@ -115,7 +115,7 @@ process(uclk_i)
s_count_ones_c <= (others =>'0'); s_count_ones_c <= (others =>'0');
else else
if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
s_count_ones_c <= (others =>'0'); -- counter initialized s_count_ones_c <= (others =>'0'); -- counter initialized
elsif rx_data_i = '1' then -- counting the number of ones elsif rx_data_i = '1' then -- counting the number of ones
......
wf_rx_osc.vhd → wf_rx_tx_osc.vhd
View file @ a702526a
--================================================================================================= --=================================================================================================
--! @file wf_rx_osc.vhd --! @file wf_rx_tx_osc.vhd
--================================================================================================= --=================================================================================================
--! Standard library --! Standard library
...@@ -12,13 +12,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -12,13 +12,13 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- wf_rx_osc //change name to wf_rx_tx_osc -- -- wf_rx_tx_osc --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name wf_rx_osc -- unit name wf_rx_tx_osc
-- --
--! @brief Generation the clock signals needed for the transmiter and receiver units. \n --! @brief Generation the clock signals needed for the transmiter and receiver units. \n
--! --!
...@@ -79,10 +79,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions ...@@ -79,10 +79,10 @@ use IEEE.NUMERIC_STD.all; --! conversion functions
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_rx_osc --! Entity declaration for wf_rx_tx_osc
--================================================================================================= --=================================================================================================
entity wf_rx_osc is entity wf_rx_tx_osc is
generic (C_COUNTER_LENGTH : integer := 11; -- in the slowest bit rate (31.25kbps), the period is generic (C_COUNTER_LENGTH : integer := 11; -- in the slowest bit rate (31.25kbps), the period is
-- 32000ns and can be measured after 1280 uclk ticks. -- 32000ns and can be measured after 1280 uclk ticks.
-- Therefore a counter of 11 bits is the max needed -- Therefore a counter of 11 bits is the max needed
...@@ -96,7 +96,7 @@ entity wf_rx_osc is ...@@ -96,7 +96,7 @@ entity wf_rx_osc is
uclk_i : in std_logic; --! 40 MHz clock uclk_i : in std_logic; --! 40 MHz clock
rate_i : in std_logic_vector (1 downto 0); --! bit rate rate_i : in std_logic_vector (1 downto 0); --! bit rate
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signals from wf_tx_rx -- Signals from wf_tx_rx
...@@ -123,18 +123,18 @@ entity wf_rx_osc is ...@@ -123,18 +123,18 @@ entity wf_rx_osc is
-- bits is expected -- bits is expected
-- Output signals needed in the transmission -- Output signals needed in the transmission
tx_clk_p_buff_o : out std_logic_vector(C_CLKFCDLENTGTH -1 downto 0); tx_clk_p_buff_o : out std_logic_vector (C_CLKFCDLENTGTH -1 downto 0);
tx_clk_o : out std_logic tx_clk_o : out std_logic
); );
end entity wf_rx_osc; end entity wf_rx_tx_osc;
--================================================================================================= --=================================================================================================
--! architecture declaration --! architecture declaration
--================================================================================================= --=================================================================================================
architecture rtl of wf_rx_osc is architecture rtl of wf_rx_tx_osc is
-- calculations of the number of uclk ticks equivalent to the reception/ transmission period -- calculations of the number of uclk ticks equivalent to the reception/ transmission period
...@@ -156,7 +156,7 @@ architecture rtl of wf_rx_osc is ...@@ -156,7 +156,7 @@ architecture rtl of wf_rx_osc is
-- auxiliary signals declarations -- auxiliary signals declarations
signal s_counter_rx, s_counter_tx, s_period, s_jitter : unsigned (C_COUNTER_LENGTH-1 downto 0); signal s_counter_rx, s_counter_tx, s_period, s_jitter : unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_counter_full, s_one_forth_period, s_half_period :unsigned (C_COUNTER_LENGTH-1 downto 0); signal s_counter_full, s_one_forth_period, s_half_period :unsigned (C_COUNTER_LENGTH-1 downto 0);
signal s_tx_clk_p_buff : std_logic_vector(C_CLKFCDLENTGTH -1 downto 0); signal s_tx_clk_p_buff : std_logic_vector (C_CLKFCDLENTGTH -1 downto 0);
signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic; signal s_tx_clk_d1, s_tx_clk, s_tx_clk_p : std_logic;
signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic; signal s_rx_bit_clk, s_rx_bit_clk_d1, s_rx_manch_clk, s_rx_manch_clk_d1 : std_logic;
signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic; signal s_adjac_bits_edge_found, s_signif_edge_found : std_logic;
......
status_gen.vhd → wf_status_bytes_gen.vhd
View file @ a702526a
This diff is collapsed.
wf_tx.vhd
View file @ a702526a
...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -41,7 +41,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! wf_engine \n --! wf_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! reset_logic \n --! wf_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
-- --
-- --
...@@ -55,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -55,7 +55,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! -> v0.02 PAS Entity Ports added, start of architecture content --! -> v0.02 PAS Entity Ports added, start of architecture content
--! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit --! -> v0.03 EG timing changes; tx_clk_p_buff_i got 1 more bit
--! briefly index_offset_i needed to arrive 1 clock tick earlier --! briefly byte_index_i needed to arrive 1 clock tick earlier
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
...@@ -75,7 +75,7 @@ entity wf_tx is ...@@ -75,7 +75,7 @@ entity wf_tx is
-- user interface general signals -- user interface general signals
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
-- Signal from the reset_logic unit -- Signal from the wf_reset_unit unit
nFIP_rst_i : in std_logic; --! internal reset nFIP_rst_i : in std_logic; --! internal reset
-- Signals from the wf_engine_control -- Signals from the wf_engine_control
...@@ -88,11 +88,11 @@ entity wf_tx is ...@@ -88,11 +88,11 @@ entity wf_tx is
-- crc bytes follow -- crc bytes follow
-- Signals from the wf_produced_vars -- Signals from the wf_produced_vars
byte_i : in std_logic_vector(7 downto 0); byte_i : in std_logic_vector (7 downto 0);
--! data byte to be delivered --! data byte to be delivered
-- Signal from the wf_rx_tx_osc -- Signal from the wf_rx_tx_osc
tx_clk_p_buff_i : in std_logic_vector(C_CLKFCDLENTGTH-1 downto 0); tx_clk_p_buff_i : in std_logic_vector (C_CLKFCDLENTGTH-1 downto 0);
--! clk for transmission synchronization --! clk for transmission synchronization
-- OUTPUTS -- OUTPUTS
...@@ -125,9 +125,9 @@ architecture rtl of wf_tx is ...@@ -125,9 +125,9 @@ architecture rtl of wf_tx is
signal s_bit_index_load, s_decr_index : std_logic; signal s_bit_index_load, s_decr_index : std_logic;
signal s_bit_index_is_zero : std_logic; signal s_bit_index_is_zero : std_logic;
signal s_bit_index, s_bit_index_top : unsigned(4 downto 0); signal s_bit_index, s_bit_index_top : unsigned(4 downto 0);
signal s_byte : std_logic_vector(7 downto 0); signal s_byte : std_logic_vector (7 downto 0);
signal s_manchester_crc : std_logic_vector(31 downto 0); signal s_manchester_crc : std_logic_vector (31 downto 0);
signal s_crc_byte_manch, s_byte_manch : std_logic_vector(15 downto 0); signal s_crc_byte_manch, s_byte_manch : std_logic_vector (15 downto 0);
--================================================================================================= --=================================================================================================
...@@ -156,10 +156,10 @@ begin ...@@ -156,10 +156,10 @@ begin
--! finally a combinatorial process to manage the output signals), which are the 3 processes that --! finally a combinatorial process to manage the output signals), which are the 3 processes that
--! follow. --! follow.
--! The signal tx_clk_p_buff_i is used for the synchronization of the transitions of the state --! The signal tx_clk_p_buff_i is used for the synchronization of the state transitions of the
--! machine as well as the actions on the output signals. --! machine as well as of the actions on the output signals.
-- The following draft drawing shows the transitions of the signal tx_clk_p_buff_i with respect to -- The following drawing shows the transitions of the signal tx_clk_p_buff_i with respect to
-- the signal tx_clk (line driver half bit clock). -- the signal tx_clk (line driver half bit clock).
-- tx_clk: __________|----------------|________________|----------------|_______________ -- tx_clk: __________|----------------|________________|----------------|_______________
...@@ -174,7 +174,7 @@ begin ...@@ -174,7 +174,7 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "idle state": signals initializations -- "idle state": signals initializations
-- jump to "send_fss" state after a pulse arrival from the signal start_produce_p_i (controlled by the -- jump to "send_fss" state after a pulse on the signal start_produce_p_i (controlled by the
-- wf_engine_control) -- wf_engine_control)
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
...@@ -189,9 +189,9 @@ begin ...@@ -189,9 +189,9 @@ begin
-- the tx_clk_p_buff(3) assertion. -- the tx_clk_p_buff(3) assertion.
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- "send_data_byte state": delivery of manchester encoded bits of data that arrive from the -- "send_data_byte" state: delivery of manchester encoded bits of data that arrive from the
-- wf_produced_vars unit (byte_i), with the coordination of the wf_engine_control (byte_ready_p_i) -- wf_produced_vars unit (byte_i), with the coordination of the wf_engine_control (byte_ready_p_i)
-- request of a new byte on tx_clk_p_buff (0) assertion -- request of a new byte on tx_clk_p_buff (0) assertion (with s_bit_index = 0)
-- bit delivery after tx_clk_p_buff (1) assertion -- bit delivery after tx_clk_p_buff (1) assertion
-- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1)) -- new byte available after tx_clk_p_buff (2) assertion (to be sent on the next tx_clk_p_buff (1))
-- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times -- s_bit_index updated after tx_clk_p_buff (3) assertion (the s_bit_index here loops several times
...@@ -202,7 +202,7 @@ begin ...@@ -202,7 +202,7 @@ begin
-- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index -- start_produce_p_i signal; for the rest, there is a request of a new byte when the s_bit_index
-- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal -- arrives to zero and on the assertion of the tx_clk_p_buff (0). A pulse on the request_byte signal
-- triggers the wf_control_engine to send a new address to the memory of the produced_vars unit (new -- triggers the wf_control_engine to send a new address to the memory of the produced_vars unit (new
-- address available on tx_clk_p_buff (1)), which in turn will give an output one uclk cycle later
-- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of -- (on tx_clk_p_buff (2)), exactly on the assertion of the byte_ready_p_i. Finally the first bit of
-- this new byte starts being delivered after tx_clk_p_buff (3) assertion. -- this new byte starts being delivered after tx_clk_p_buff (3) assertion.
......
wf_tx_rx.vhd
View file @ a702526a
...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -28,7 +28,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! On reception it depacketises the data and only presents the actual data --! On reception it depacketises the data and only presents the actual data
--! contents. It also verifies the FCS (Frame Checksum, CRC).\n --! contents. It also verifies the FCS (Frame Checksum, CRC).\n
--! On transmission it packetises the data and adds the FCS. --! On transmission it packetises the data and adds the FCS.
--! The unit wf_rx_osc recovers the carrier clock during --! The unit wf_rx_tx_osc recovers the carrier clock during
--! --!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- --
...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -42,7 +42,7 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
--! wf_engine \n --! wf_engine \n
--! tx_engine \n --! tx_engine \n
--! clk_gen \n --! clk_gen \n
--! reset_logic \n --! wf_reset_unit \n
--! consumed_ram \n --! consumed_ram \n
--! --!
--! --!
...@@ -69,25 +69,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c ...@@ -69,25 +69,26 @@ use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, c
entity wf_tx_rx is entity wf_tx_rx is
port ( port (
uclk_i : in std_logic; --! User Clock uclk_i : in std_logic; --! User Clock
nFIP_rst_i : in std_logic; nFIP_rst_i : in std_logic;
start_produce_p_i : in std_logic; reset_rx_unit_p_i : in std_logic;
request_byte_p_o : out std_logic; start_produce_p_i : in std_logic;
byte_ready_p_i : in std_logic; request_byte_p_o : out std_logic;
byte_i : in std_logic_vector(7 downto 0); byte_ready_p_i : in std_logic;
last_byte_p_i : in std_logic; byte_i : in std_logic_vector (7 downto 0);
tx_data_o : out std_logic; last_byte_p_i : in std_logic;
tx_enable_o : out std_logic; d_a_i : in std_logic;
d_clk_o : out std_logic; rate_i : in std_logic_vector (1 downto 0);
d_a_i : in std_logic; tx_data_o : out std_logic;
rate_i : in std_logic_vector(1 downto 0); tx_enable_o : out std_logic;
byte_ready_p_o : out std_logic; d_clk_o : out std_logic;
byte_o : out std_logic_vector(7 downto 0); byte_ready_p_o : out std_logic;
last_byte_p_o : out std_logic; byte_o : out std_logic_vector (7 downto 0);
fss_decoded_p_o : out std_logic; last_byte_p_o : out std_logic;
fss_decoded_p_o : out std_logic;
code_violation_p_o : out std_logic; code_violation_p_o : out std_logic;
crc_wrong_p_o : out std_logic; crc_wrong_p_o : out std_logic;
crc_ok_p_o : out std_logic crc_ok_p_o : out std_logic
); );
end entity wf_tx_rx; end entity wf_tx_rx;
...@@ -103,15 +104,15 @@ architecture rtl of wf_tx_rx is ...@@ -103,15 +104,15 @@ architecture rtl of wf_tx_rx is
constant C_CLKFCDLENTGTH : natural := 4; constant C_CLKFCDLENTGTH : natural := 4;
signal s_data_in_d3 : std_logic_vector(2 downto 0); signal s_data_in_d3 : std_logic_vector (2 downto 0);
signal s_data_in_r_edge, s_data_in_f_edge : std_logic; signal s_data_in_r_edge, s_data_in_f_edge : std_logic;
signal s_d_filtered : std_logic; signal s_d_filtered : std_logic;
signal s_first_fe : std_logic; signal s_first_fe : std_logic;
signal s_clk_carrier_p : std_logic; signal s_clk_carrier_p : std_logic;
signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic; signal s_clk_bit_180_p, s_sample_bit_p, s_sample_manch_bit_p : std_logic;
signal s_edge_window, edge_180_window : std_logic; signal s_edge_window, edge_180_window : std_logic;
signal s_data_in_edge, s_code_violation : std_logic; signal s_data_in_edge : std_logic;
signal s_clk_fixed_carrier_p_d : std_logic_vector(C_CLKFCDLENTGTH - 1 downto 0); signal s_clk_fixed_carrier_p_d : std_logic_vector (C_CLKFCDLENTGTH - 1 downto 0);
begin begin
...@@ -155,6 +156,7 @@ begin ...@@ -155,6 +156,7 @@ begin
PORT MAP( PORT MAP(
uclk_i => uclk_i, uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
reset_rx_unit_p_i => reset_rx_unit_p_i,
byte_ready_p_o => byte_ready_p_o, byte_ready_p_o => byte_ready_p_o,
byte_o => byte_o, byte_o => byte_o,
last_byte_p_o => last_byte_p_o, last_byte_p_o => last_byte_p_o,
...@@ -173,7 +175,7 @@ begin ...@@ -173,7 +175,7 @@ begin
); );
uwf_rx_osc :wf_rx_osc uwf_rx_osc :wf_rx_tx_osc
generic map(C_COUNTER_LENGTH => 11, generic map(C_COUNTER_LENGTH => 11,
C_QUARTZ_PERIOD => 24.8, C_QUARTZ_PERIOD => 24.8,
...@@ -195,7 +197,7 @@ begin ...@@ -195,7 +197,7 @@ begin
rx_adjac_bits_window_o => edge_180_window rx_adjac_bits_window_o => edge_180_window
); );
Udeglitcher : deglitcher Udeglitcher : wf_rx_deglitcher
generic map (C_ACULENGTH => 10) generic map (C_ACULENGTH => 10)
Port map( uclk_i => uclk_i, Port map( uclk_i => uclk_i,
nFIP_rst_i => nFIP_rst_i, nFIP_rst_i => nFIP_rst_i,
......
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