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nanoFIP - Gateware
Commit d6fdf0fd authored by egousiou's avatar egousiou
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major changes in wf_produced and wf_tx 

changes also in reset_logic, after first testing with test bench asking for a produced var.

git-svn-id: http://svn.ohwr.org/cern-fip/trunk/hdl/design@63 7f0067c9-7624-46c7-bd39-3fb5400c0213
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DualClkRAM.vhd
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NanoFip.pdc
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...@@ -105,10 +105,10 @@ set_io {c_id_i[3]} \ ...@@ -105,10 +105,10 @@ set_io {c_id_i[3]} \
-DIRECTION Input -DIRECTION Input
#set_io cyc_i \ set_io cyc_i \
# -pinname 75 \ -pinname 75 \
# -fixed yes \ -fixed yes \
# -DIRECTION Input -DIRECTION Input
set_io {dat_i[0]} \ set_io {dat_i[0]} \
...@@ -333,10 +333,10 @@ set_io fd_wdgn_i \ ...@@ -333,10 +333,10 @@ set_io fd_wdgn_i \
-DIRECTION Input -DIRECTION Input
#set_io fx_rxa_i \ set_io fx_rxa_i \
# -pinname 121 \ -pinname 121 \
# -fixed yes \ -fixed yes \
# -DIRECTION Inout -DIRECTION Input
set_io fx_rxd_i \ set_io fx_rxd_i \
......
deglitcher.vhd
View file @ d6fdf0fd
--=========================================================================== --=================================================================================================
--! @file deglitcher.vhd --! @file deglitcher.vhd
--! @brief Glitch filter. 1 pulse adapted filter. --=================================================================================================
--===========================================================================
--! Standard library --! Standard library
library IEEE; library IEEE;
--! Standard packages --! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions use IEEE.NUMERIC_STD.all; --! conversion functions
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- deglitcher -- -- deglitcher --
-- -- -- --
-- CERN, BE/CO/HT -- -- CERN, BE/CO/HT --
-- -- -- --
------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--
-- unit name eglitcher
--
--! @brief Glitch filter. 1 pulse adapted filter.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
-- --
-- unit name: deglitcher
-- --
--! @brief Glitch filter. 1 pulse adapted filter. -- @date 08/2010
--! --
--! --
--! --! @version v0.03
--!
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--!
--! @date 10/08/2009
-- --
--! @version v0.01
-- --
--! @details --! @details
--! --
--! <b>Dependencies:</b>\n --! \n<b>Dependencies:</b>\n
--! wf_engine \n --! wf_osc \n
--! tx_engine \n --! reset_logic \n
--! clk_gen \n --
--! reset_logic \n --
--! consumed_ram \n --! \n<b>Modified by:</b>\n
--! --! Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch) \n
--! --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! <b>References:</b>\n --
--! ---------------------------------------------------------------------------------------------------
--! --
--! --! \n\n<b>Last changes:</b>\n
--! <b>Modified by:</b>\n --! 07/08/2009 v0.02 PAS Entity Ports added, start of architecture content
--! Author: Pablo Alvarez Sanchez --! 23/08/2010 v0.03 EG Signal names changed, delayed signals changed, code cleaned-up
------------------------------------------------------------------------------- --
--! \n\n<b>Last changes:</b>\n ---------------------------------------------------------------------------------------------------
--! 07/08/2009 v0.02 PAAS Entity Ports added, start of architecture content --
--! --! @todo
------------------------------------------------------------------------------- -- more comments
--! @todo Define I/O signals \n ---------------------------------------------------------------------------------------------------
--!
-------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for wf_deglitcher
--============================================================================ --=================================================================================================
--! Entity declaration for deglitcher
--============================================================================
entity deglitcher is entity deglitcher is
Generic (C_ACULENGTH : integer := 10); generic (C_ACULENGTH : integer := 10);
Port ( uclk_i : in STD_LOGIC;
rx_data_i : in STD_LOGIC; port(
clk_bit_180_p_i : in std_logic; -- INPUTS
rx_data_filtered_o : out STD_LOGIC; -- User interface general signal
carrier_p_i : in STD_LOGIC; uclk_i : in std_logic; --! 40 MHz clock
sample_manch_bit_p_o : out STD_LOGIC;
sample_bit_p_o : out STD_LOGIC -- Signal from the reset_logic unit
); nFIP_rst_i : in std_logic; --! internal reset
-- FIELDRIVE input signal
rx_data_i : in std_logic; --! buffered fd_rxd
-- Signals from the wf_osc unit
sample_bit_p_i : in std_logic; --! pulsed signal signaling a new bit
sample_manch_bit_p_i : in std_logic; --! pulsed signal signaling a new manchestered bit
-- OUTPUTS
-- Output signals needed for the receiverwf_rx
sample_bit_p_o : out std_logic;
rx_data_filtered_o : out std_logic;
sample_manch_bit_p_o : out std_logic
);
end deglitcher; end deglitcher;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture Behavioral of deglitcher is architecture Behavioral of deglitcher is
signal s_onesc : signed(C_ACULENGTH - 1 downto 0); signal s_count_ones_c : signed(C_ACULENGTH - 1 downto 0);
signal s_rx_data_filtered_o: STD_LOGIC; signal s_rx_data_filtered: STD_LOGIC;
signal s_d_d: std_logic_vector(2 downto 0);
signal s_rx_data_filtered_d : std_logic; signal s_rx_data_filtered_d : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin begin
---------------------------------------------------------------------------------------------------
process(uclk_i) process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if carrier_p_i = '1' then -- 4 clock ticks after a transition of manchestered input
s_onesc <= to_signed(0,s_onesc'length); if nFIP_rst_i = '1' then
elsif rx_data_i = '1' then s_count_ones_c <= (others =>'0');
s_onesc <= s_onesc - 1; else
else
s_onesc <= s_onesc + 1; if sample_manch_bit_p_i = '1' then -- arrival of a new manchester bit
end if; s_count_ones_c <= (others =>'0'); -- counter initialized
end if;
end process;
elsif rx_data_i = '1' then -- counting the number of ones
s_count_ones_c <= s_count_ones_c - 1;
else
s_count_ones_c <= s_count_ones_c + 1;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
process(uclk_i) process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if carrier_p_i = '1' then
s_rx_data_filtered_o <= s_onesc(s_onesc'left); if nFIP_rst_i = '1' then
s_rx_data_filtered <= '0';
s_rx_data_filtered_d <= '0';
else
if sample_manch_bit_p_i = '1' then
s_rx_data_filtered <= s_count_ones_c (s_count_ones_c'left); -- if the ones are more than
-- the zeros, the output is 1
-- otherwise, 0
end if; end if;
s_rx_data_filtered_d <= s_rx_data_filtered_o;
s_rx_data_filtered_d <= s_rx_data_filtered;
end if;
end if; end if;
end process; end process;
sample_manch_bit_p_o <= carrier_p_i; rx_data_filtered_o <= s_rx_data_filtered_d;
sample_bit_p_o <= clk_bit_180_p_i; sample_manch_bit_p_o <= sample_manch_bit_p_i;
sample_bit_p_o <= sample_bit_p_i;
--process(carrier_p_i)
--begin
--if rising_edge(carrier_p_i) then
-- s_rx_data_filtered_o <= s_onesc(s_onesc'left);
-- elsif falling_edge(carrier_p_i) then
-- s_rx_data_filtered_o <= s_onesc(s_onesc'left);
-- end if;
-- end process;
--process(uclk_i)
--begin
--if rising_edge(uclk_i) then
-- sample_manch_bit_p_o <= carrier_p_i;
-- sample_bit_p_o <= clk_bit_180_p_i; ---- delay on clk_bit_180_p_i, so that sample_bit is 1 clock tick before rx_data_filtered_o
-- s_rx_data_filtered_o_1 <= s_rx_data_filtered_o_0;
-- s_rx_data_filtered_o_0 <= s_rx_data_filtered_o;
-- end if;
--end process;
rx_data_filtered_o <= s_rx_data_filtered_d;
end Behavioral;
end Behavioral;
--=================================================================================================
-- architecture end
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
......
dpblockram_clka_rd_clkb_wr_syn.vhd
View file @ d6fdf0fd
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @file dpblockram.vhd --! @file dpblockram_clka_rd_clkb_wr_syn.vhd
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! Standard library
-- Standard library
library IEEE; library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
-- Standard packages
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions
---------------------------------------------------------------------------------------------------
-- --
-- dpblockram_clka_rd_clkb_wr_syn --
-- --
-- CERN, BE/CO/HT --
-- --
---------------------------------------------------------------------------------------------------
--
-- unit name dpblockram.vhd
--
--
--! @brief The unit provides, transparently to the outside world, the memory triplication.
--! The component DualClkRam (512 bytes) is triplicated; each incoming byte is written
--! at the same position in the three memories, whereas each outgoing byte is the
--! outcome of a majority voter.
--
--
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--
--
--! @date 08/2010
--
--
--! @version v0.1
--
--
--! @details\n
--
--! \n<b>Dependencies:</b>\n
--! DualClkRAM.vhd \n
--
--
--! \n<b>Modified by:</b>\n
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch) \n
--
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
-- --
-- CERN, BE --
-- --
---------------------------------------------------------------------------------------------------
-- --
-- unit name: dpblockram.vhd --! \n\n<b>Last changes: </b>\n
-- --! -> code cleaned-up and commented
--! @brief The unit provides transparently to the outside world the memory triplication and all the --
--! associated actions.
--!
--!
--! @author <Pablo Alvarez(pablo.alvarez.sanchez@cern.ch)>
--
--! @date 24\01\2009
--
--! @version 1
--!
--! @details The component DualClkRam is triplicated.
--! Each incoming byte is written at the same position in the three memories, whereas
--! each outgoing byte is the outcome of a majority voting system from the three memories.
--!
--! <b>Dependencies:</b>\n
--! DualClkRAM.vhd \n
--!
--! <b>References:</b>\n
--!
--! <b>Modified by:</b>\n
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--
--! @todo --! @todo
-- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--=================================================================================================
--! Entity declaration for dpblockram_clka_rd_clkb_wr_syn
--=================================================================================================
entity dpblockram_clka_rd_clkb_wr is entity dpblockram_clka_rd_clkb_wr is
generic (c_data_length : integer := 8; -- 8: length of data word generic (c_data_length : integer := 8; -- 8: length of data word (1 byte)
c_addr_length : integer := 9); -- 2^9: memory depth c_addr_length : integer := 9); -- 2^9: memory depth (512 bytes)
port ( port (
...@@ -61,6 +80,9 @@ entity dpblockram_clka_rd_clkb_wr is ...@@ -61,6 +80,9 @@ entity dpblockram_clka_rd_clkb_wr is
end dpblockram_clka_rd_clkb_wr; end dpblockram_clka_rd_clkb_wr;
--=================================================================================================
--! architecture declaration
--=================================================================================================
architecture syn of dpblockram_clka_rd_clkb_wr is architecture syn of dpblockram_clka_rd_clkb_wr is
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
...@@ -84,15 +106,16 @@ architecture syn of dpblockram_clka_rd_clkb_wr is ...@@ -84,15 +106,16 @@ architecture syn of dpblockram_clka_rd_clkb_wr is
end component DualClkRam; end component DualClkRam;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
signal zero : std_logic;
signal one : std_logic;
signal s_rwB : std_logic;
signal s_zeros : std_logic_vector(7 downto 0);
type t_data_o_A_array is array (natural range <>) of std_logic_vector(7 downto 0); type t_data_o_A_array is array (natural range <>) of std_logic_vector(7 downto 0);
signal data_o_A_array : t_data_o_A_array(0 to 2); --will keep the DOUTA of each one of the memories
---------------------------------------------------------------------------------------------------
signal data_o_A_array : t_data_o_A_array(0 to 2); -- keeps the DOUTA of each one of the memories
signal zero, one, s_rwB : std_logic;
signal s_zeros : std_logic_vector(7 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin begin
zero <= '0'; zero <= '0';
...@@ -107,7 +130,7 @@ s_rwB <= not write_en_B_i; ...@@ -107,7 +130,7 @@ s_rwB <= not write_en_B_i;
--! The input DINB is written in the same position in the 3 memories. --! The input DINB is written in the same position in the 3 memories.
--! The output DOUTA from each memory is kept in the array data_o_A_array. --! The output DOUTA from each memory is kept in the array data_o_A_array.
memory_triplication: for I in 0 to 2 generate G_memory_triplication: for I in 0 to 2 generate
UDualClkRam : DualClkRam UDualClkRam : DualClkRam
port map ( DINA => s_zeros, port map ( DINA => s_zeros,
...@@ -126,7 +149,8 @@ UDualClkRam : DualClkRam ...@@ -126,7 +149,8 @@ UDualClkRam : DualClkRam
DOUTB => open) ; DOUTB => open) ;
end generate; end generate;
---------------------------------------------------------------------------------------------------
--without memory triplication:
--UDualClkRam : DualClkRam --UDualClkRam : DualClkRam
-- port map ( DINA => s_zeros, -- port map ( DINA => s_zeros,
-- ADDRA => addr_A_i, -- ADDRA => addr_A_i,
...@@ -144,15 +168,18 @@ end generate; ...@@ -144,15 +168,18 @@ end generate;
-- DOUTB => open) ; -- DOUTB => open) ;
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief: majority voter after a memory reading --!@brief majority voter: when a reading is done from the memory, the output of the unit is the
--! when a reading is done from the memory, the process majority_voter considers internally the --! output of the majority voter. The majority voter considers the outputs of the three memories
--! outputs of the three memories and defines as final output, the majority of the three. --! and "calculates" their majority with combinatorial logic.
majority_voter: process (data_o_A_array) majority_voter: data_A_o <= (data_o_A_array(0) and data_o_A_array(1)) or
begin (data_o_A_array(1) and data_o_A_array(2)) or
data_A_o <= (data_o_A_array(0) and data_o_A_array(1)) or (data_o_A_array(2) and data_o_A_array(0));
(data_o_A_array(1) and data_o_A_array(2)) or
(data_o_A_array(2) and data_o_A_array(0)); end syn;
end process; --=================================================================================================
-- architecture end
end syn; --=================================================================================================
\ No newline at end of file ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
nanofip.vhd
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reset_logic.vhd
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status_gen.vhd
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wf_consumed_vars.vhd
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wf_crc.vhd
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wf_dec_m_ids.vhd
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--=========================================================================== --===========================================================================
--! @file wf_produced_vars.vhd --! @file wf_dec_m_ids.vhd
--! @brief Nanofip control unit
--=========================================================================== --===========================================================================
--! Standard library
--! standard library
library IEEE; library IEEE;
--! Standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions --! standard packages
use IEEE.NUMERIC_STD.all; --! conversion functions use IEEE.STD_LOGIC_1164.all; --! std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions
use work.wf_package.all;
--! specific packages -- not needed i t hink, confirm
------------------------------------------------------------------------------- --use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
-- --
-- wf_produced_vars -- ---------------------------------------------------------------------------------------------------
-- -- -- --
-- CERN, BE/CO/HT -- -- wf_dec_m_ids --
-- -- -- --
------------------------------------------------------------------------------- -- CERN, BE/CO/HT --
-- -- --
-- unit name: wf_produced_vars ---------------------------------------------------------------------------------------------------
-- --
--! @brief Nanofip control unit. It provides with a transparent interface between the wf_control state machine and the RAM and special \n -- unit name wf_dec_m_ids
--! variable bytes not stored in RAM. wf_wishbone has write access and wf_control read access.\n --
--! --
--! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) --! @brief Decoding of the inputs S_ID and M_ID and construction of the nanoFIP output S_ID
-- --! (identification selection)
--! @date 11/09/2009 --
--! --
--! @version v0.01 --! @author Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! --! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--! @details --
--! --! @date 08/2010
--! <b>Dependencies:</b>\n --
--! wf_package \n --
--! --! @version v0.02
--! --
--! <b>References:</b>\n --
--! --! @details\n
--! --
--! --! \n<b>Dependencies:</b>\n
--! <b>Modified by:</b>\n --
--! Author: Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch) --
------------------------------------------------------------------------------- --! \n<b>Modified by:</b>\n
--! Pablo Alvarez Sanchez (pablo.alvarez.sanchez@cern.ch)
--! Evangelia Gousiou (evangelia.gousiou@cern.ch)
--
---------------------------------------------------------------------------------------------------
--
--! \n\n<b>Last changes:</b>\n --! \n\n<b>Last changes:</b>\n
--! 11/09/2009 v0.01 EB First version \n --! -> 11/09/2009 v0.01 EB First version \n
--! --! -> 20/08/2010 v0.02 EG code cleaned-up \n
------------------------------------------------------------------------------- --
---------------------------------------------------------------------------------------------------
--
--! @todo --! @todo
--! --! -> understand whazz goin on!
------------------------------------------------------------------------------- --! -> chane name of the unit
--
---------------------------------------------------------------------------------------------------
--============================================================================ --=================================================================================================
--! Entity declaration for wf_dec_m_ids --! Entity declaration for wf_dec_m_ids
--============================================================================ --=================================================================================================
entity wf_dec_m_ids is entity wf_dec_m_ids is
port ( port (
uclk_i : in std_logic; --! User Clock -- INPUTS
rst_i : in std_logic; -- User Interface general signal
uclk_i : in std_logic;
s_id_o : out std_logic_vector(1 downto 0); -- Signal from the reset_logic unit
--! Identification variable settings. nFIP_rst_i : in std_logic;
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification settings
--! Constructor identification settings. -- WorldFIP settings
c_id_dec_o : out std_logic_vector (7 downto 0); --! Constructor identification setting m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
c_id_i : in std_logic_vector (3 downto 0); --! Constructor identification settings
--! Identification variable settings.
m_id_i : in std_logic_vector (3 downto 0); --! Model identification settings
--! Constructor identification settings.
c_id_i : in std_logic_vector (3 downto 0) --! Constructor identification settings
-- OUTPUTS
-- WorldFIP settings nanoFIP output
s_id_o : out std_logic_vector(1 downto 0); --! Identification selection
-- Output to wf_produced_vars
m_id_dec_o : out std_logic_vector (7 downto 0); --! Model identification decoded
c_id_dec_o : out std_logic_vector (7 downto 0) --! Constructor identification decoded
); );
end entity wf_dec_m_ids; end entity wf_dec_m_ids;
...@@ -83,11 +92,9 @@ end entity wf_dec_m_ids; ...@@ -83,11 +92,9 @@ end entity wf_dec_m_ids;
------------------------------------------------------------------------------- --=================================================================================================
------------------------------------------------------------------------------- --! architecture declaration
--! ARCHITECTURE OF wf_dec_m_ids --=================================================================================================
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture rtl of wf_dec_m_ids is architecture rtl of wf_dec_m_ids is
...@@ -96,6 +103,10 @@ architecture rtl of wf_dec_m_ids is ...@@ -96,6 +103,10 @@ architecture rtl of wf_dec_m_ids is
signal s_c_even, s_c_odd : std_logic_vector(3 downto 0); signal s_c_even, s_c_odd : std_logic_vector(3 downto 0);
signal s_load_val : std_logic; signal s_load_val : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin begin
s_c_n <= s_c + 1; s_c_n <= s_c + 1;
...@@ -104,7 +115,7 @@ begin ...@@ -104,7 +115,7 @@ begin
P_dec:process(uclk_i) P_dec:process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
s_m_even <= (others => '0'); s_m_even <= (others => '0');
s_c_even <= (others => '0'); s_c_even <= (others => '0');
...@@ -130,7 +141,11 @@ begin ...@@ -130,7 +141,11 @@ begin
s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2))); s_id_o <= std_logic_vector(s_c((s_c'left - 1) downto (s_c'left - 2)));
end architecture rtl; end architecture rtl;
------------------------------------------------------------------------------- --=================================================================================================
-- E N D O F F I L E -- architecture end
------------------------------------------------------------------------------- --=================================================================================================
\ No newline at end of file ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_engine_control.vhd
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wf_package.vhd
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wf_produced_vars.vhd
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wf_rx.vhd
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--================================================================================================= --=================================================================================================
--! @file wf_rx.vhd --! @file wf_rx.vhd
--! @brief Deserialises the WorldFIP data
--================================================================================================= --=================================================================================================
--! Standard library
-- standard library
library IEEE; library IEEE;
--! Standard packages -- standard packages
use IEEE.STD_LOGIC_1164.all; --! std_logic definitions use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; --! conversion functions use IEEE.NUMERIC_STD.all; -- conversion functions
use work.wf_package.all; --! specific packages
use work.WF_PACKAGE.all; --! definitions of supplemental types, subtypes, constants
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- -- -- --
...@@ -19,62 +20,63 @@ use work.wf_package.all; ...@@ -19,62 +20,63 @@ use work.wf_package.all;
-- -- -- --
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- --
-- unit name: wf_rx
-- --
--! @brief Deserialisation of the input signal fd_rxd (buffered) and construction of bytes of data --! @brief Deserialisation of the input signal fd_rxd (buffered) and construction of bytes of data
--! to be provided to the wf_consumed unit. --! to be provided to the wf_consumed unit.
--!
--!
--!
--! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--!
--! @date 08/2010
-- --
--! @version v0.02
-- --
--! @details --! @author Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
--! --! Evangelia Gousiou (Evangelia.Gousiou@cern.ch)
--! <b>Dependencies:</b>\n --
--! wf_rx_tx_osc\n --
--! wf_deglitcher\n --! @date 08/2010
--! wf_tx_rx\n --
--! --
--! --! @version v0.02
--! --
--! --
--! <b>References:</b>\n --! @details \n
--! --
--! --! \n<b>Dependencies:</b>\n
--! --! wf_rx_tx_osc\n
--! <b>Modified by:</b>\n --! wf_deglitcher\n
--! Author: Erik van der Bij --! wf_tx_rx \n
--! Pablo Alvarez Sanchez --
--! Evangelia Gousiou --
--------------------------------------------------------------------------------------------------- --! \n<b>Modified by:</b>\n
--! \n\n<b>Last changes:</b>\n --! Erik van der Bij \n
--! 07/10 state switch_to_deglitched added --! Pablo Alvarez Sanchez \n
--! output signal wait_d_first_f_edge_o added --! Evangelia Gousiou \n
--! signals renamed --
--! code cleaned-up + commented ---------------------------------------------------------------------------------------------------
--! --
--! \n\n<b>Last changes:</b>\n
--! -> state switch_to_deglitched added
--! -> output signal wait_d_first_f_edge_o added
--! -> signals renamed
--! -> code cleaned-up + commented
--
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--! @todo Define I/O signals \n --
--! --! @todo
--! ->
--
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--================================================================================================= --=================================================================================================
--! Entity declaration for wf_rx --! Entity declaration for wf_rx
--================================================================================================= --=================================================================================================
entity wf_rx is entity wf_rx is
port ( port (
-- Inputs -- INPUTS
-- user interface general signals -- User interface general signal
uclk_i : in std_logic; --! 40MHz clock uclk_i : in std_logic; --! 40MHz clock
rst_i : in std_logic; --! global reset
-- Signal from the reset_logic unit
nFIP_rst_i : in std_logic; --! internal reset
-- signals from the wf_rx_tx_osc -- signals from the wf_rx_tx_osc
signif_edge_window_i : in std_logic; --! time window where a significant edge is expected signif_edge_window_i : in std_logic; --! time window where a significant edge is expected
...@@ -92,7 +94,7 @@ entity wf_rx is ...@@ -92,7 +94,7 @@ entity wf_rx is
sample_bit_p_i : in std_logic; --! sample_bit_p_i : in std_logic; --!
-- Outputs -- OUTPUTS
-- needed by the wf_consumed and wf_engine_control -- needed by the wf_consumed and wf_engine_control
byte_ready_p_o : out std_logic; --! indication of a valid data byte byte_ready_p_o : out std_logic; --! indication of a valid data byte
...@@ -115,12 +117,9 @@ entity wf_rx is ...@@ -115,12 +117,9 @@ entity wf_rx is
end entity wf_rx; end entity wf_rx;
--=================================================================================================
--------------------------------------------------------------------------------------------------- --! architecture declaration
--------------------------------------------------------------------------------------------------- --=================================================================================================
--! rtl architecture of wf_rx
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
architecture rtl of wf_rx is architecture rtl of wf_rx is
-- states of the receiver's state machine -- states of the receiver's state machine
...@@ -129,7 +128,7 @@ architecture rtl of wf_rx is ...@@ -129,7 +128,7 @@ architecture rtl of wf_rx is
-- signals -- signals
signal rx_st, nx_rx_st : rx_st_t; signal rx_st, nx_rx_st : rx_st_t;
signal pointer, s_start_pointer : unsigned(4 downto 0); signal pointer, s_start_pointer : unsigned(3 downto 0);
signal s_decr_pointer, s_load_pointer, s_pointer_is_zero : std_logic; signal s_decr_pointer, s_load_pointer, s_pointer_is_zero : std_logic;
signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_rx_data_filtered_f_edge : std_logic; signal s_sample_bit_p_d1, s_sample_bit_p_d2, s_rx_data_filtered_f_edge : std_logic;
...@@ -150,21 +149,24 @@ architecture rtl of wf_rx is ...@@ -150,21 +149,24 @@ architecture rtl of wf_rx is
signal s_rx_data_filtered_buff : std_logic_vector(1 downto 0); signal s_rx_data_filtered_buff : std_logic_vector(1 downto 0);
--=================================================================================================
-- architecture begin
--=================================================================================================
begin begin
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
--!@brief instantiation of the crc calculator unit --!@brief instantiation of the crc calculator unit
cmp_wf_crc : wf_crc crc_verification : wf_crc
generic map( generic map(
c_poly_length => 16) c_GENERATOR_POLY_length => 16)
port map( port map(
uclk_i => uclk_i, uclk_i => uclk_i,
rst_i => rst_i, nFIP_rst_i => nFIP_rst_i,
start_p_i => s_start_crc_p, start_crc_p_i => s_start_crc_p,
d_rdy_p_i => s_write_bit_to_byte, data_bit_ready_p_i => s_write_bit_to_byte,
d_i => rx_data_filtered_i, data_bit_i => rx_data_filtered_i,
crc_o => open, crc_o => open,
crc_rdy_p_o => open,
crc_ok_p => s_crc_ok_p crc_ok_p => s_crc_ok_p
); );
...@@ -185,7 +187,7 @@ architecture rtl of wf_rx is ...@@ -185,7 +187,7 @@ architecture rtl of wf_rx is
Receiver_FSM_Sync: process(uclk_i) Receiver_FSM_Sync: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
rx_st <= idle; rx_st <= idle;
else else
rx_st <= nx_rx_st; rx_st <= nx_rx_st;
...@@ -461,7 +463,7 @@ architecture rtl of wf_rx is ...@@ -461,7 +463,7 @@ architecture rtl of wf_rx is
Frame_End_Detector: process(uclk_i) Frame_End_Detector: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
s_frame_end_detection <= '1'; s_frame_end_detection <= '1';
elsif s_pointer_is_zero = '1' and sample_manch_bit_p_i = '1' then elsif s_pointer_is_zero = '1' and sample_manch_bit_p_i = '1' then
...@@ -479,7 +481,7 @@ architecture rtl of wf_rx is ...@@ -479,7 +481,7 @@ architecture rtl of wf_rx is
Incoming_Bits_Pointer: process(uclk_i) Incoming_Bits_Pointer: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
pointer <= (others => '0'); pointer <= (others => '0');
else else
...@@ -500,7 +502,7 @@ architecture rtl of wf_rx is ...@@ -500,7 +502,7 @@ architecture rtl of wf_rx is
Append_Bit_To_Byte: process (uclk_i) Append_Bit_To_Byte: process (uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
s_byte <= (others => '0'); s_byte <= (others => '0');
else else
...@@ -515,7 +517,7 @@ architecture rtl of wf_rx is ...@@ -515,7 +517,7 @@ architecture rtl of wf_rx is
process(uclk_i) process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
s_crc_ok <= '0'; s_crc_ok <= '0';
else else
...@@ -537,7 +539,7 @@ architecture rtl of wf_rx is ...@@ -537,7 +539,7 @@ architecture rtl of wf_rx is
Detect_f_edge_rx_data_filtered: process(uclk_i) Detect_f_edge_rx_data_filtered: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
s_rx_data_filtered_buff <= (others => '0'); s_rx_data_filtered_buff <= (others => '0');
s_rx_data_filtered_f_edge <= '0'; s_rx_data_filtered_f_edge <= '0';
else else
...@@ -564,7 +566,7 @@ end process; ...@@ -564,7 +566,7 @@ end process;
Check_code_violations: process(uclk_i) Check_code_violations: process(uclk_i)
begin begin
if rising_edge(uclk_i) then if rising_edge(uclk_i) then
if rst_i = '1' then if nFIP_rst_i = '1' then
byte_ready_p_o <= '0'; byte_ready_p_o <= '0';
s_violation_check <='0'; s_violation_check <='0';
s_rx_data_filtered_d <='0'; s_rx_data_filtered_d <='0';
...@@ -588,7 +590,11 @@ end process; ...@@ -588,7 +590,11 @@ end process;
crc_ok_p_o <= s_frame_end_detected_p and s_crc_ok; crc_ok_p_o <= s_frame_end_detected_p and s_crc_ok;
crc_wrong_p_o <= s_frame_end_detected_p and (not s_crc_ok); crc_wrong_p_o <= s_frame_end_detected_p and (not s_crc_ok);
end architecture rtl; end architecture rtl;
--=================================================================================================
-- architecture end
--=================================================================================================
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
-- E N D O F F I L E -- E N D O F F I L E
--------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------
\ No newline at end of file
wf_rx_osc.vhd
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wf_tx.vhd
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wf_tx_rx.vhd
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