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cd1d3c31
Commit
cd1d3c31
authored
Mar 21, 2012
by
Grzegorz Daniluk
Committed by
Alessandro Rubini
Mar 28, 2012
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spec: add pps_gen
parent
40691583
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3 changed files
with
126 additions
and
6 deletions
+126
-6
pps_gen.c
arch-spec/dev/pps_gen.c
+93
-0
pps_gen_regs.h
arch-spec/include/hw/pps_gen_regs.h
+21
-6
pps_gen.h
arch-spec/include/pps_gen.h
+12
-0
No files found.
arch-spec/dev/pps_gen.c
0 → 100644
View file @
cd1d3c31
#include "../spec.h"
//#include <inttypes.h>
#include <hw/pps_gen_regs.h>
#define PPS_PULSE_WIDTH 100000
static
inline
void
ppsg_writel
(
uint32_t
reg
,
uint32_t
data
)
{
*
(
volatile
uint32_t
*
)
(
BASE_PPSGEN
+
reg
)
=
data
;
}
static
inline
uint32_t
ppsg_readl
(
uint32_t
reg
)
{
return
*
(
volatile
uint32_t
*
)(
BASE_PPSGEN
+
reg
);
}
void
pps_gen_init
()
{
uint32_t
cr
;
cr
=
PPSG_CR_CNT_EN
|
PPSG_CR_PWIDTH_W
(
PPS_PULSE_WIDTH
);
ppsg_writel
(
PPSG_REG_CR
,
cr
);
ppsg_writel
(
PPSG_REG_ESCR
,
0
);
ppsg_writel
(
PPSG_REG_ADJ_UTCLO
,
100
);
ppsg_writel
(
PPSG_REG_ADJ_UTCHI
,
0
);
ppsg_writel
(
PPSG_REG_ADJ_NSEC
,
0
);
ppsg_writel
(
PPSG_REG_CR
,
cr
|
PPSG_CR_CNT_SET
);
ppsg_writel
(
PPSG_REG_CR
,
cr
);
}
void
pps_gen_adjust_nsec
(
int32_t
how_much
)
{
TRACE_DEV
(
"ADJ: nsec %d nanoseconds
\n
"
,
how_much
);
#if 1
ppsg_writel
(
PPSG_REG_ADJ_UTCLO
,
0
);
ppsg_writel
(
PPSG_REG_ADJ_UTCHI
,
0
);
ppsg_writel
(
PPSG_REG_ADJ_NSEC
,
(
how_much
/
8
));
ppsg_writel
(
PPSG_REG_CR
,
PPSG_CR_CNT_EN
|
PPSG_CR_PWIDTH_W
(
PPS_PULSE_WIDTH
)
|
PPSG_CR_CNT_ADJ
);
#endif
}
void
pps_gen_adjust_utc
(
int32_t
how_much
)
{
#if 1
TRACE_DEV
(
"ADJ: utc %d seconds
\n
"
,
how_much
);
ppsg_writel
(
PPSG_REG_ADJ_UTCLO
,
how_much
);
ppsg_writel
(
PPSG_REG_ADJ_UTCHI
,
0
);
ppsg_writel
(
PPSG_REG_ADJ_NSEC
,
0
);
ppsg_writel
(
PPSG_REG_CR
,
PPSG_CR_CNT_EN
|
PPSG_CR_PWIDTH_W
(
PPS_PULSE_WIDTH
)
|
PPSG_CR_CNT_ADJ
);
#endif
}
int
pps_gen_busy
()
{
return
ppsg_readl
(
PPSG_REG_CR
)
&
PPSG_CR_CNT_ADJ
?
0
:
1
;
}
void
pps_gen_get_time
(
uint32_t
*
utc
,
uint32_t
*
cntr_nsec
)
{
uint32_t
cyc_before
,
cyc_after
;
uint32_t
utc_lo
;
do
{
cyc_before
=
ppsg_readl
(
PPSG_REG_CNTR_NSEC
)
&
0xfffffff
;
utc_lo
=
ppsg_readl
(
PPSG_REG_CNTR_UTCLO
)
;
cyc_after
=
ppsg_readl
(
PPSG_REG_CNTR_NSEC
)
&
0xfffffff
;
}
while
(
cyc_after
<
cyc_before
);
delay
(
100000
);
if
(
utc
)
*
utc
=
utc_lo
;
if
(
cntr_nsec
)
*
cntr_nsec
=
cyc_after
;
}
void
pps_gen_enable_output
(
int
enable
)
{
if
(
enable
)
ppsg_writel
(
PPSG_REG_ESCR
,
PPSG_ESCR_PPS_VALID
|
PPSG_ESCR_TM_VALID
);
else
ppsg_writel
(
PPSG_REG_ESCR
,
0
);
}
arch-spec/include/hw/pps_gen_regs.h
View file @
cd1d3c31
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File :
../../../software/include/hw/
pps_gen_regs.h
* Author : auto-generated by wbgen2 from
wrsw_pps_gen
.wb
* Created : S
at Sep 11 22:22:55 2010
* File : pps_gen_regs.h
* Author : auto-generated by wbgen2 from
pps_gen_wb
.wb
* Created : S
un Oct 30 01:54:53 2011
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
wrsw_pps_gen
.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE
pps_gen_wb
.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
#ifndef __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#define __WBGEN2_REGDEFS_PPS_GEN_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
...
...
@@ -60,6 +62,17 @@
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
/* [0x0]: REG Control Register */
#define PPSG_REG_CR 0x00000000
/* [0x4]: REG Nanosecond counter register */
...
...
@@ -74,4 +87,6 @@
#define PPSG_REG_ADJ_UTCLO 0x00000014
/* [0x18]: REG UTC Adjustment register (most-significant part) */
#define PPSG_REG_ADJ_UTCHI 0x00000018
/* [0x1c]: REG External sync control register */
#define PPSG_REG_ESCR 0x0000001c
#endif
arch-spec/include/pps_gen.h
0 → 100644
View file @
cd1d3c31
#ifndef __PPS_GEN_H
#define __PPS_GEN_H
#include <inttypes.h>
void
pps_gen_init
();
void
pps_gen_adjust_nsec
(
int32_t
how_much
);
void
shw_pps_gen_adjust_utc
(
int32_t
how_much
);
int
pps_gen_busy
();
void
pps_gen_get_time
(
uint32_t
*
utc
,
uint32_t
*
cntr_nsec
);
#endif
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