Commit b7d3e9e6 authored by Matthieu Cattin's avatar Matthieu Cattin

fmc_adc: Fix (svec specific) functions name.

parent 9d93e5ae
...@@ -898,13 +898,13 @@ class CFmcAdc100m: ...@@ -898,13 +898,13 @@ class CFmcAdc100m:
# Write data to DDR # Write data to DDR
# carrier_addr is in 32-bit word # carrier_addr is in 32-bit word
# data must be a array of 32-bit words # data must be a array of 32-bit words
def get_data(self, carrier_addr, data): def put_data(self, carrier_addr, data):
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr) self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, carrier_addr)
for i in range(len(data)): for i in range(len(data)):
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, data[i]) self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, data[i])
# Clear DDR # Clear DDR
def get_data(self): def clear_ddr(self):
self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, 0x0) self.bus.iwrite(0, self.DDR_ADR_ADDR, 4, 0x0)
for i in range(0x4000000): for i in range(0x4000000):
self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, 0x0) self.bus.iwrite(0, self.DDR_DAT_ADDR, 4, 0x0)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment