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Benoit Rat authoredc4a2585a
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ddr3_model_c5.v | ||
ddr3_model_parameters_c5.vh | ||
ddr_controller_bank5.prj | ||
isim.sh | ||
isim.tcl | ||
readme.txt | ||
sim.do | ||
sim_tb_top.vhd | ||
timing_sim.sh |
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isim.sh | Loading commit data... | |
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readme.txt | Loading commit data... | |
sim.do | Loading commit data... | |
sim_tb_top.vhd | Loading commit data... | |
timing_sim.sh | Loading commit data... |