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Benoit Rat authoredc4a2585a
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| ddr3_ctrl_spec_bank3_32b_32b.prj | ||
| ddr3_model_c3.v | ||
| ddr3_model_parameters_c3.vh | ||
| isim.sh | ||
| isim.tcl | ||
| readme.txt | ||
| sim.do | ||
| sim_tb_top.vhd | ||
| timing_sim.sh |
| Name |
Last commit
|
Last update |
|---|---|---|
| .. | ||
| ddr3_ctrl_spec_bank3_32b_32b.prj | ||
| ddr3_model_c3.v | ||
| ddr3_model_parameters_c3.vh | ||
| isim.sh | ||
| isim.tcl | ||
| readme.txt | ||
| sim.do | ||
| sim_tb_top.vhd | ||
| timing_sim.sh |