Design and Layout Review 15/04/2016
15 April 2016, 10h - 12h, 774-2-058
Present
Remi Dobin (Trimble), Alex Belarbi (Trimble), Richard Day (Trimble), Kinali Attila (external), Serrano Javier (BE/CO), Calvo Giraldo Eva (BE/CO), Gonzalez Cobas David (BE/CO), Bouhired-Ferrag Denia (BE/CO), Daniluk Grzegorz (BE/CO), Van der Bij Erik (BE/CO), Arruat Michel (BE/CO), Lampridis Dimitrios (BE/CO), Wlostowski Tomasz (BE/CO), Gousiou Evangelia (BE/CO), Belleman Jeroen (BE/BI), Gasior Marek (BE/BI)
General description of the design
The goal of the ADC board is to transform the incoming analog signals in digital data. These incoming signals are coming from an other board which converts the pulses into an oscillating analog signal.
These converted data are sent to the MicroZed, an FPGA prototyping board. The ADC board is used as a carrier card for the MicroZed. As all the FPGA's GPIO are not used by the ADC, some connectors around the board allow the user to use them.
To have the best possible resolution, we paid attention to the noise while designing the board. For further information, see the Quick-design-explanation wiki page.
Detailed comments on schematics
General remarks
- Avoid crossing the wires (use labels)
- OHL text in all corners of the pages. Put it on all pages in the same place.
- Each symbol should be the precise order number. Now clock splitter is only in a note that should use -1 version
- Add a thermometer to be able to control the temperature influence
Sheet 1 : ADC Board
- Avoid using the bus connections on the main hierarchical page. It is better to make them on the sub-pageand then to route the bus on the main page. That makes the connections easier to read.
- Put connectors on that schematic
Sheet 2: Power supplies
- Add the nominal current at the input
- Capacitors marked Cin1-Cin11 and Cout1-Cout10. Number normally (C1 etc). Same for Rset1, Cbias1 etc.
- Comment Vout (MAX) = -> Vout =, should remove the "MAX" or should be a min value also
- Specify PGFP = IN: “power good and fast start-up functionalities are not needed”
- How are heatsinks fixed?
- Put a figure of the used heatsink on the schematic
- Put a comment on for the two bridges
- Use symbol of Schottky diodes, while likely use normal ones.
- Specify Diodes used.
Sheet 3 & 4: ADC and inputs
- Add TVS on all inputs
- As the input are always the same circuit, make an hierarchical page for them.
- What is the signalling rate of the ADC digital output? Mention in comment on schematics page. Is that compatible to the max rate of the MicroZED?
- Remove the labels for the same net (AVDD1-AVDD6)
- Resistor values marked as 30E, 200E, 49E9 -> 49R9, 30
- Over-design of decoupling. Make it simpler, 10nF not needed. But suggest to add an inductor. (Cf. ADC100M: just two 100nF and 4.7uH inductor: 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range) measured, while it has 4 channels and full front-end. AD9645 spec: SNR = 74 dBFS (to Nyquist).)
- Specify input range
- Specify transformer type and tell which winding ratio.
- Why 30 Ohm and not 33 Ohm as specified in datasheet on VINA/B?
- Why not use a 4-channel ADC so that there can be no skew problems?
Sheet 5: ADC Clock splitter
- Note of version IC: add below component.
- Max speed 300 MHz, specify on schematics
- Repeat table of input filter. Tell what are the default settings.
- J1 not specified what type of connector.
- As want to sample with 125 MHz, and max 300MHz on splitter, may possibly limit.
- Why no local clock oscillator and require a stable external one? Add one.
- Use a power splitter instead of a clock splitter IC
- Link the filter inputs to vcc using pull-ups to have a default configuration
Sheet 6: Connections to the MicroZED board
- What are all L1-L6 etc? Not specified.
- Why are the double labels for? Makes schematics look weird.
- Maybe add some buffers between the ADC and the FPGA
Sheet 7: Connections to the MicroZED board 2
- 10nF not of much use as connectors to it. Better have 10uF as is consuming a lot and may have large peaks
- Why comment PG_MODULE?
- Banks that are not used for the ADC should be connected to the 3.3 V instead of 1.8 V (more common)
- Add a reset switch on the pin CARRIER_SRST (see carrier card datasheet)
- Add a note concerning the MicroZed compatibilities
Sheet 8: Connectors on the side of the board
- Remove some GPIO connections (40 pins are enough)
- Put the GPIO connectors to be compatible with designs done for the MicroZed GPIO carrier card
Bill of Materials
- Made by hand and not extracted from schematics. Prone to errors when modifying.
- Missing manufacturer name
- Very expensive components used everywhere. Almost 100 Euro on C and R alone.
- Really 0.1% needed?
- 16 C values (ADC100M: 12 C values, and has a full front-end) (R: 9 types, ADC100M 18, so is good)
- MicroZED should likely be put on BOM
- Why two types of SMA?
- Prices, have fixed two digits (69, 4.6, 0.58)
Comments on the layout
- Avoid small angles while crossing the tracks (better to cross with 90°)
- Avoid to cross the power junction with the differential tracks (local impedance mismatch)
- Put the decoupling capacitors on the top of the board if possible.
- Bigger distance between the SMA connectors to be able to screw the male connector easier
Other Comments on the written documentation: "Realisation of a low noise acquisition board : design choices"
- Missing name of author.
- Choices not made clear (The minimum specifications are 12 bits with an LVDS output.)
- Texas InstrumentS, some French words used, some typos (MicroZeb Board)
Conclusions
Thanks to all the participants for making this review a very interesting and instructive one. This meeting is definitely an important one for the project progress. In addition to the small remarks concerning the good practices of realising such a design, we have discussed some bigger design choices.
Following these discussions, we decided to make some changes on the design. The biggest of these changes is the replacement of the ADC. Using a 4 input channels one would, obviously, make the design easier.