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Simple VME FMC Carrier SVEC
Commit 347107a6 authored by Tristan Gingold's avatar Tristan Gingold
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svec_vmecore_test_top: update comments for PLL.

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hdl/top/vmecore_test/svec_vmecore_test_top.vhd
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...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch> -- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT) -- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19 -- Created : 2017-09-19
-- Last update: 2017-11-27 -- Last update: 2017-12-05
-- Standard : VHDL'93 -- Standard : VHDL'93
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Description: Top-level file for the test design . -- Description: Top-level file for the test design .
...@@ -242,10 +242,10 @@ begin -- architecture top ...@@ -242,10 +242,10 @@ begin -- architecture top
DIVCLK_DIVIDE => 1, DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000, CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 62.5 MHz CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 62.5 MHz CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000, CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8, CLKOUT2_DIVIDE => 8,
......
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