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Simple VME FMC Carrier SVEC
Commits
4b314172
Commit
4b314172
authored
Sep 28, 2017
by
Tristan Gingold
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test_vme: check DMA writes.
parent
b81f25cc
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2 changed files
with
59 additions
and
16 deletions
+59
-16
vmecore_test.vhd
hdl/top/vmecore_test/vmecore_test.vhd
+44
-16
test_vme.c
software/vmecore_test/test_vme.c
+15
-0
No files found.
hdl/top/vmecore_test/vmecore_test.vhd
View file @
4b314172
...
...
@@ -20,10 +20,15 @@ entity vmecore_test is
end
vmecore_test
;
architecture
rtl
of
vmecore_test
is
-- Memory map:
-- 0 - 0x1ff: sram (512B)
-- Memory map
(WB addresses, multiply by 4 to get VME addresses)
:
-- 0 - 0x1ff: sram (512
*4
B)
-- 0x1000: leds (4B)
-- 0x2000: counter (4B). Generate a timeout when 0 is reached.
-- 0x1001: last WB transaction (see the code for the format)
-- 0x1002: nbr of WB read accesses (write to clear)
-- 0x1003: nbr of WB write accesses (likewise)
-- 0x1004: nbr of write errors in pattern ram
-- 0x2000: counter (4B). Generate an interrupt when 0 is reached.
-- 0x3000: pattern ram (0x1000 * 4B)
signal
counter
:
unsigned
(
31
downto
0
);
signal
leds
:
std_logic_vector
(
15
downto
0
);
...
...
@@ -31,12 +36,20 @@ architecture rtl of vmecore_test is
signal
nbr_read
:
unsigned
(
15
downto
0
);
signal
nbr_write
:
unsigned
(
15
downto
0
);
signal
nbr_write_errors
:
unsigned
(
31
downto
0
);
signal
pattern
:
std_logic_vector
(
31
downto
0
);
type
sram_type
is
array
(
0
to
16
#
1
ff
#
)
of
std_logic_vector
(
31
downto
0
);
signal
sram
:
sram_type
;
begin
pattern
(
31
downto
16
)
<=
not
slave_i
.
adr
(
15
downto
0
);
pattern
(
15
downto
0
)
<=
slave_i
.
adr
(
15
downto
0
);
process
(
clk_sys_i
)
variable
idx
:
natural
;
variable
err
:
boolean
;
begin
if
rising_edge
(
clk_sys_i
)
then
slave_o
.
ack
<=
'0'
;
...
...
@@ -47,6 +60,7 @@ begin
leds
<=
(
others
=>
'0'
);
nbr_read
<=
(
others
=>
'0'
);
nbr_write
<=
(
others
=>
'0'
);
nbr_write_errors
<=
(
others
=>
'0'
);
else
-- Decrementer
if
counter
/=
(
counter
'range
=>
'0'
)
then
...
...
@@ -73,20 +87,22 @@ begin
end
if
;
end
loop
;
when
"01"
=>
case
slave_i
.
adr
(
1
downto
0
)
is
when
"00"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"00
0
"
=>
for
i
in
1
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
leds
(
8
*
i
+
7
downto
8
*
i
)
<=
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
);
end
if
;
end
loop
;
when
"01"
=>
when
"0
0
1"
=>
null
;
when
"10"
=>
when
"
0
10"
=>
nbr_read
<=
(
others
=>
'0'
);
when
"11"
=>
when
"
0
11"
=>
nbr_write
<=
(
others
=>
'0'
);
when
"100"
=>
nbr_write_errors
<=
(
others
=>
'0'
);
when
others
=>
null
;
end
case
;
...
...
@@ -98,7 +114,18 @@ begin
end
if
;
end
loop
;
when
"11"
=>
null
;
err
:
=
false
;
for
i
in
3
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
and
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
)
/=
pattern
(
8
*
i
+
7
downto
8
*
i
))
then
err
:
=
true
;
end
if
;
end
loop
;
if
err
then
nbr_write_errors
<=
nbr_write_errors
+
1
;
end
if
;
when
others
=>
null
;
end
case
;
...
...
@@ -111,26 +138,27 @@ begin
idx
:
=
to_integer
(
unsigned
(
slave_i
.
adr
(
8
downto
0
)));
slave_o
.
dat
<=
sram
(
idx
);
when
"01"
=>
case
slave_i
.
adr
(
1
downto
0
)
is
when
"00"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"00
0
"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
leds
;
when
"01"
=>
when
"0
0
1"
=>
slave_o
.
dat
<=
(
31
downto
21
=>
'0'
)
&
last_trans
;
when
"10"
=>
when
"
0
10"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_read
);
when
"11"
=>
when
"
0
11"
=>
slave_o
.
dat
(
31
downto
16
)
<=
(
others
=>
'0'
);
slave_o
.
dat
(
15
downto
0
)
<=
std_logic_vector
(
nbr_write
);
when
"100"
=>
slave_o
.
dat
<=
std_logic_vector
(
nbr_write_errors
);
when
others
=>
null
;
end
case
;
when
"10"
=>
slave_o
.
dat
<=
std_logic_vector
(
counter
);
when
"11"
=>
slave_o
.
dat
(
31
downto
16
)
<=
not
slave_i
.
adr
(
15
downto
0
);
slave_o
.
dat
(
15
downto
0
)
<=
slave_i
.
adr
(
15
downto
0
);
slave_o
.
dat
<=
pattern
;
when
others
=>
null
;
end
case
;
...
...
software/vmecore_test/test_vme.c
View file @
4b314172
...
...
@@ -265,6 +265,18 @@ do_test_dma (uint8_t am)
int
s
;
struct
timespec
start_ts
;
// Clear pattern write error counter
map_for_am
(
0x39
);
ptr32
[
0x1004
]
=
0
;
report
(
ptr32
[
0x1004
]
==
0
,
"write error counter correctly reset"
);
ptr32
[
0x3000
]
=
0x12345678
;
report
(
swapbe32
(
ptr32
[
0x1004
])
==
1
,
"write error counter is working (on error)"
);
ptr32
[
0x3000
]
=
swapbe32
(
0xcfff3000
);
report
(
swapbe32
(
ptr32
[
0x1004
])
==
1
,
"write error counter is working (on correct)"
);
ptr32
[
0x1004
]
=
0
;
printf
(
"INFO: test DMA for am 0x%02x
\n
"
,
am
);
base
=
map_for_am
(
am
);
...
...
@@ -346,6 +358,9 @@ do_test_dma (uint8_t am)
report
(
s
==
0
,
"DMA write"
);
free
(
buf
);
map_for_am
(
0x39
);
report
(
ptr32
[
0x1004
]
==
0
,
"no write error during DMA"
);
}
static
void
...
...
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