svec7: test project

90348ce2 · Tomasz Wlostowski · 41415b81 · 90348ce2 · 90348ce2 · 90348ce2
Commit 90348ce2 authored Oct 18, 2019 by Tomasz Wlostowski
15 changed files
--- a/hdl/rtl/svec7/Manifest.py
+++ b/hdl/rtl/svec7/Manifest.py
+files = [
+    "../svec_base_regs.vhd",
+    "svec7_base_wr.vhd",
+    "litedram_core.v"
+]
--- a/hdl/rtl/svec7/litedram_core.init
+++ b/hdl/rtl/svec7/litedram_core.init
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--- a/hdl/rtl/svec7/litedram_core.v
+++ b/hdl/rtl/svec7/litedram_core.v
--- a/hdl/rtl/svec7/svec7_base_wr.vhd
+++ b/hdl/rtl/svec7/svec7_base_wr.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- SVEC
+-- https://ohwr.org/projects/svec
+--------------------------------------------------------------------------------
+--
+-- unit name:   svec_base_wr
+--
+-- description: SVEC carrier base, with WR.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2019
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.vme64x_pkg.all;
+use work.wr_xilinx_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_svec_pkg.all;
+use work.buildinfo_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.streamers_pkg.all;
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity svec7_base_wr is
+  generic (
+    --  If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
+    g_WITH_VIC      : boolean := True;
+    g_WITH_ONEWIRE  : boolean := True;
+    g_WITH_SPI      : boolean := True;
+    g_WITH_WR       : boolean := False;
+    g_WITH_DDR      : boolean := True;
+    --  Address of the application meta-data.  0 if none.
+    g_APP_OFFSET    : std_logic_vector(31 downto 0) := x"0000_0000";
+    --  Number of user interrupts
+    g_NUM_USER_IRQ  : natural := 1;
+    --  WR PTP firmware.
+    g_DPRAM_INITF   : string := "../../../../wr-cores/bin/wrpc/wrc_phy16.bram";
+    -- Number of aux clocks syntonized by WRPC to WR timebase
+    g_AUX_CLKS : integer := 0;
+    -- Fabric interface selection for WR Core:
+    -- plain     = expose WRC fabric interface
+    -- streamers = attach WRC streamers to fabric interface
+    -- etherbone = attach Etherbone slave to fabric interface
+    g_FABRIC_IFACE  : t_board_fabric_iface := plain;
+    -- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
+    g_STREAMERS_OP_MODE  : t_streamers_op_mode  := TX_AND_RX;
+    g_TX_STREAMER_PARAMS : t_tx_streamer_params := c_TX_STREAMER_PARAMS_DEFAUT;
+    g_RX_STREAMER_PARAMS : t_rx_streamer_params := c_RX_STREAMER_PARAMS_DEFAUT;
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the testbench.
+    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
+    g_SIMULATION : integer := 0;
+    -- Increase information messages during simulation
+    g_VERBOSE    : boolean := False
+  );
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Reset from system fpga
+    rst_n_i : in std_logic;
+
+    -- 125 MHz PLL reference
+    clk_62m5_pllref_p_i : in std_logic;
+    clk_62m5_pllref_n_i : in std_logic;
+
+    -- 20MHz VCXO clock (for WR)
+    clk_20m_vcxo_i : in std_logic := '0';
+
+    -- 125 MHz GTX reference
+    clk_125m_gtx_n_i : in std_logic := '0';
+    clk_125m_gtx_p_i : in std_logic := '0';
+
+    
+    -- Aux clocks, which can be disciplined by the WR Core
+    clk_aux_i : in  std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
+
+    -- 10MHz ext ref clock input
+    clk_10m_ext_i : in std_logic := '0';
+    -- External PPS input
+    pps_ext_i     : in std_logic := '0';
+
+    ---------------------------------------------------------------------------
+    -- VME interface
+    ---------------------------------------------------------------------------
+
+    vme_write_n_i    : in    std_logic;
+    vme_sysreset_n_i : in    std_logic;
+    vme_retry_oe_o   : out   std_logic;
+    vme_retry_n_o    : out   std_logic;
+    vme_lword_n_b    : inout std_logic;
+    vme_iackout_n_o  : out   std_logic;
+    vme_iackin_n_i   : in    std_logic;
+    vme_iack_n_i     : in    std_logic;
+    vme_gap_i        : in    std_logic;
+    vme_dtack_oe_o   : out   std_logic;
+    vme_dtack_n_o    : out   std_logic;
+    vme_ds_n_i       : in    std_logic_vector(1 downto 0);
+    vme_data_oe_n_o  : out   std_logic;
+    vme_data_dir_o   : out   std_logic;
+    vme_berr_o       : out   std_logic;
+    vme_as_n_i       : in    std_logic;
+    vme_addr_oe_n_o  : out   std_logic;
+    vme_addr_dir_o   : out   std_logic;
+    vme_irq_o        : out   std_logic_vector(7 downto 1);
+    vme_ga_i         : in    std_logic_vector(4 downto 0);
+    vme_data_b       : inout std_logic_vector(31 downto 0);
+    vme_am_i         : in    std_logic_vector(5 downto 0);
+    vme_addr_b       : inout std_logic_vector(31 downto 1);
+
+    ---------------------------------------------------------------------------
+    -- FMC interface
+    ---------------------------------------------------------------------------
+
+    -- I2C interface for accessing FMC EEPROM.
+    fmc0_scl_b : inout std_logic;
+    fmc0_sda_b : inout std_logic;
+    fmc1_scl_b : inout std_logic;
+    fmc1_sda_b : inout std_logic;
+
+    -- Presence  (there is a pull-up)
+    fmc0_prsnt_m2c_n_i: in std_logic;
+    fmc1_prsnt_m2c_n_i: in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Carrier
+    ---------------------------------------------------------------------------
+
+    -- Onewire interface
+    onewire_b : inout std_logic;
+
+    -- Carrier I2C eeprom
+    carrier_scl_b : inout std_logic;
+    carrier_sda_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Flash memory SPI interface
+    ---------------------------------------------------------------------------
+
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic := '1';
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SPI interface to DACs
+    ---------------------------------------------------------------------------
+
+    plldac_sclk_o     : out std_logic;
+    plldac_din_o      : out std_logic;
+    pll20dac_din_o    : out std_logic;
+    pll20dac_sclk_o   : out std_logic;
+    pll20dac_sync_n_o : out std_logic;
+    pll25dac_din_o    : out std_logic;
+    pll25dac_sclk_o   : out std_logic;
+    pll25dac_sync_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic := '0';
+    sfp_rxn_i         : in    std_logic := '0';
+    sfp_mod_def0_i    : in    std_logic := '0';          -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;          -- scl
+    sfp_mod_def2_b    : inout std_logic;          -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic := '0';
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic := '0';
+
+    ------------------------------------------
+    -- DDR 
+    ------------------------------------------
+    ddr_a_o       : out   std_logic_vector(14 downto 0);
+    ddr_ba_o      : out   std_logic_vector(2 downto 0);
+    ddr_cas_n_o   : out   std_logic;
+    ddr_ck_n_o    : out   std_logic;
+    ddr_ck_p_o    : out   std_logic;
+    ddr_cke_o     : out   std_logic;
+    ddr_dq_b      : inout std_logic_vector(63 downto 0);
+    ddr_dqs_n_b  : inout std_logic_vector(7 downto 0);
+    ddr_dqs_p_b  : inout std_logic_vector(7 downto 0);
+    ddr_odt_o     : out   std_logic;
+    ddr_ras_n_o   : out   std_logic;
+    ddr_reset_n_o : out   std_logic;
+    ddr_rzq_b     : inout std_logic;
+    ddr_dm_o     : out   std_logic_vector(7 downto 0);
+    ddr_we_n_o    : out   std_logic;
+    ddr_cs_n_o    : out   std_logic;
+
+
+    -- PCB revision
+    pcbrev_i : in std_logic_vector(4 downto 0);
+
+    ------------------------------------------
+    --  User part
+    ------------------------------------------
+
+    --  Direct access to the DDR-3
+    --  Classic wishbone
+    ddr_clk_i   : in  std_logic := '0';
+    ddr_rst_n_i : in  std_logic := '1';
+    ddr_axi4_i    : in  t_axi4_full_master_out_512;
+    ddr_axi4_o    : out t_axi4_full_master_in_512;
+
+    --  Clocks and reset.
+    clk_sys_62m5_o    : out std_logic;
+    rst_sys_62m5_n_o  : out std_logic;
+    clk_ref_62m5_o    : out std_logic;
+    rst_ref_62m5_n_o  : out std_logic;
+
+    -- 125 MHz DDMTD clock output
+    clk_dmtd_62m5_o : out std_logic;
+
+    --  Interrupts
+    irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
+
+    -- WR fabric interface (when g_fabric_iface = "plain")
+    wrf_src_o : out t_wrf_source_out;
+    wrf_src_i : in  t_wrf_source_in := c_DUMMY_SRC_IN;
+    wrf_snk_o : out t_wrf_sink_out;
+    wrf_snk_i : in  t_wrf_sink_in   := c_DUMMY_SNK_IN;
+
+    -- WR streamers (when g_fabric_iface = "streamers")
+    wrs_tx_data_i  : in  std_logic_vector(g_TX_STREAMER_PARAMS.DATA_WIDTH-1 downto 0) := (others => '0');
+    wrs_tx_valid_i : in  std_logic := '0';
+    wrs_tx_dreq_o  : out std_logic;
+    wrs_tx_last_i  : in  std_logic := '1';
+    wrs_tx_flush_i : in  std_logic := '0';
+    wrs_tx_cfg_i   : in  t_tx_streamer_cfg := c_TX_STREAMER_CFG_DEFAULT;
+    wrs_rx_first_o : out std_logic;
+    wrs_rx_last_o  : out std_logic;
+    wrs_rx_data_o  : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
+    wrs_rx_valid_o : out std_logic;
+    wrs_rx_dreq_i  : in  std_logic := '0';
+    wrs_rx_cfg_i   : in  t_rx_streamer_cfg := c_RX_STREAMER_CFG_DEFAULT;
+
+    -- Etherbone WB master interface (when g_fabric_iface = "etherbone")
+    wb_eth_master_o : out t_wishbone_master_out;
+    wb_eth_master_i : in  t_wishbone_master_in := cc_dummy_master_in;
+
+    -- Timecode I/F
+    tm_link_up_o    : out std_logic;
+    tm_time_valid_o : out std_logic;
+    tm_tai_o        : out std_logic_vector(39 downto 0);
+    tm_cycles_o     : out std_logic_vector(27 downto 0);
+
+    -- Aux clocks control
+    tm_dac_value_o       : out std_logic_vector(23 downto 0);
+    tm_dac_wr_o          : out std_logic_vector(g_AUX_CLKS-1 downto 0);
+    tm_clk_aux_lock_en_i : in  std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
+    tm_clk_aux_locked_o  : out std_logic_vector(g_AUX_CLKS-1 downto 0);
+
+    -- PPS output
+    pps_p_o    : out std_logic;
+    pps_led_o  : out std_logic;
+
+    -- Link ok indication
+    link_ok_o  : out std_logic;
+
+    -- WR leds
+    led_link_o : out std_logic;
+    led_act_o : out std_logic;
+
+    -- The wishbone bus from the gennum/host to the application
+    -- Addresses 0-0x1fff are not available (used by the carrier).
+    -- This is a pipelined wishbone with byte granularity.
+    app_wb_o           : out t_wishbone_master_out;
+    app_wb_i           : in  t_wishbone_master_in
+  );
+end entity svec7_base_wr;
+
+architecture top of svec7_base_wr is
+  -- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
+  constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
+    0      => (enabled => TRUE, bufg_en => TRUE, divide => 3),
+    others => c_AUXPLL_CFG_DEFAULT);
+
+  signal clk_sys_62m5    : std_logic;  -- 62.5Mhz
+
+  signal clk_pll_aux     : std_logic_vector(3 downto 0);
+  signal rst_pll_aux_n   : std_logic_vector(3 downto 0) := (others => '0');
+
+  --  DDR
+  signal ddr_rst         : std_logic := '1';
+
+  signal vme_wb_out     : t_wishbone_master_out;
+  signal vme_wb_in      : t_wishbone_master_in;
+
+  -- VME
+  signal vme_data_b_out    : std_logic_vector(31 downto 0);
+  signal vme_addr_b_out    : std_logic_vector(31 downto 1);
+  signal vme_lword_n_b_out : std_logic;
+  signal vme_data_dir_int  : std_logic;
+  signal vme_addr_dir_int  : std_logic;
+  signal vme_ga            : std_logic_vector(5 downto 0);
+  signal vme_berr_n        : std_logic;
+  signal vme_irq_n         : std_logic_vector(7 downto 1);
+  
+  --  The wishbone bus to the carrier part.
+  signal carrier_wb_out : t_wishbone_slave_out;
+  signal carrier_wb_in  : t_wishbone_slave_in;
+
+  signal metadata_addr : std_logic_vector(5 downto 2);
+  signal metadata_data : std_logic_vector(31 downto 0);
+
+  signal buildinfo_addr : std_logic_vector(7 downto 2);
+  signal buildinfo_data : std_logic_vector(31 downto 0);
+
+  signal therm_id_in          : t_wishbone_master_in;
+  signal therm_id_out         : t_wishbone_master_out;
+
+  -- i2c controllers to the fmcs
+  signal fmc_i2c_in           : t_wishbone_master_in;
+  signal fmc_i2c_out          : t_wishbone_master_out;
+
+  -- spi controller to the flash
+  signal flash_spi_in         : t_wishbone_master_in;
+  signal flash_spi_out        : t_wishbone_master_out;
+
+  -- vector interrupt controller
+  signal vic_in               : t_wishbone_master_in;
+  signal vic_out              : t_wishbone_master_out;
+
+  -- white-rabbit core
+  signal wrc_in               : t_wishbone_master_in;
+  signal wrc_out              : t_wishbone_master_out;
+  signal wrc_out_sh           : t_wishbone_master_out;
+
+  signal csr_rst_gbl : std_logic;
+  signal csr_rst_app : std_logic;
+
+  signal rst_csr_app_n      : std_logic;
+  signal rst_csr_app_sync_n : std_logic;
+
+  signal rst_gbl_n : std_logic;
+
+  signal fmc0_scl_out, fmc0_sda_out : std_logic;
+  signal fmc0_scl_oen, fmc0_sda_oen : std_logic;
+  signal fmc1_scl_out, fmc1_sda_out : std_logic;
+  signal fmc1_scl_oen, fmc1_sda_oen : std_logic;
+
+  signal fmc_presence : std_logic_vector(31 downto 0);
+
+  signal irq_master : std_logic;
+
+  constant num_interrupts : natural := 6 + g_NUM_USER_IRQ;
+  signal irqs : std_logic_vector(num_interrupts - 1 downto 0);
+
+  -- clock and reset
+  signal rst_sys_62m5_n : std_logic;
+  signal rst_ref_62m5_n : std_logic;
+  signal clk_ref_62m5   : std_logic;
+
+  -- I2C EEPROM
+  signal eeprom_sda_in  : std_logic;
+  signal eeprom_sda_out : std_logic;
+  signal eeprom_scl_in  : std_logic;
+  signal eeprom_scl_out : std_logic;
+
+  -- SFP
+  signal sfp_sda_in  : std_logic;
+  signal sfp_sda_out : std_logic;
+  signal sfp_scl_in  : std_logic;
+  signal sfp_scl_out : std_logic;
+
+  signal clk_dmtd_62m5 : std_logic;
+
+  signal ddr_init_done : std_logic;
+  
+  attribute keep                 : string;
+  attribute keep of clk_sys_62m5 : signal is "TRUE";
+  attribute keep of clk_ref_62m5 : signal is "TRUE";
+  attribute keep of ddr_rst       : signal is "TRUE";
+
+begin  -- architecture top
+
+  ------------------------------------------------------------------------------
+  -- VME interface
+  ------------------------------------------------------------------------------
+
+  cmp_vme_core : entity work.xvme64x_core
+    generic map (
+      g_CLOCK_PERIOD    => 16,
+      g_DECODE_AM       => TRUE,
+      g_USER_CSR_EXT    => FALSE,
+      g_WB_GRANULARITY  => BYTE,
+      g_WB_MODE         => PIPELINED,
+      g_MANUFACTURER_ID => c_CERN_ID,
+      g_BOARD_ID        => c_SVEC_ID,
+      g_REVISION_ID     => c_SVEC_REVISION_ID,
+      g_PROGRAM_ID      => c_SVEC_PROGRAM_ID)
+    port map (
+      clk_i           => clk_sys_62m5,
+      rst_n_i         => rst_sys_62m5_n,
+      vme_i.as_n      => vme_as_n_i,
+      vme_i.rst_n     => vme_sysreset_n_i,
+      vme_i.write_n   => vme_write_n_i,
+      vme_i.am        => vme_am_i,
+      vme_i.ds_n      => vme_ds_n_i,
+      vme_i.ga        => vme_ga,
+      vme_i.lword_n   => vme_lword_n_b,
+      vme_i.addr      => vme_addr_b,
+      vme_i.data      => vme_data_b,
+      vme_i.iack_n    => vme_iack_n_i,
+      vme_i.iackin_n  => vme_iackin_n_i,
+      vme_o.berr_n    => vme_berr_n,
+      vme_o.dtack_n   => vme_dtack_n_o,
+      vme_o.retry_n   => vme_retry_n_o,
+      vme_o.retry_oe  => vme_retry_oe_o,
+      vme_o.lword_n   => vme_lword_n_b_out,
+      vme_o.data      => vme_data_b_out,
+      vme_o.addr      => vme_addr_b_out,
+      vme_o.irq_n     => vme_irq_n,
+      vme_o.iackout_n => vme_iackout_n_o,
+      vme_o.dtack_oe  => vme_dtack_oe_o,
+      vme_o.data_dir  => vme_data_dir_int,
+      vme_o.data_oe_n => vme_data_oe_n_o,
+      vme_o.addr_dir  => vme_addr_dir_int,
+      vme_o.addr_oe_n => vme_addr_oe_n_o,
+      wb_o            => vme_wb_out,
+      wb_i            => vme_wb_in,
+      int_i           => irq_master);
+
+  vme_ga     <= vme_gap_i & vme_ga_i;
+  vme_berr_o <= not vme_berr_n;
+  vme_irq_o  <= not vme_irq_n;
+
+  -- VME tri-state buffers
+  vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
+  vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
+  vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
+
+  vme_addr_dir_o <= vme_addr_dir_int;
+  vme_data_dir_o <= vme_data_dir_int;
+
+  --  Mini-crossbar from vme to carrier and application bus.
+  inst_split: entity work.xwb_split
+    generic map (
+      g_mask => x"ffff_e000"
+    )
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i => rst_sys_62m5_n,
+      slave_i => vme_wb_out,
+      slave_o => vme_wb_in,
+      master_i (0) => carrier_wb_out,
+      master_i (1) => app_wb_i,
+      master_o (0) => carrier_wb_in,
+      master_o (1) => app_wb_o
+    );
+
+  inst_carrier: entity work.svec_base_regs
+    port map (
+      rst_n_i    => rst_sys_62m5_n,
+      clk_i      => clk_sys_62m5,
+      wb_cyc_i   => carrier_wb_in.cyc,
+      wb_stb_i   => carrier_wb_in.stb,
+      wb_adr_i   => carrier_wb_in.adr (12 downto 2),  -- Bytes address from vme64x core
+      wb_sel_i   => carrier_wb_in.sel,
+      wb_we_i    => carrier_wb_in.we,
+      wb_dat_i   => carrier_wb_in.dat,
+      wb_ack_o   => carrier_wb_out.ack,
+      wb_err_o   => carrier_wb_out.err,
+      wb_rty_o   => carrier_wb_out.rty,
+      wb_stall_o => carrier_wb_out.stall,
+      wb_dat_o   => carrier_wb_out.dat,
+
+      -- a ROM containing the carrier metadata
+      metadata_addr_o => metadata_addr,
+      metadata_data_i => metadata_data,
+      metadata_data_o => open,
+
+      -- offset to the application metadata
+      csr_app_offset_i    => g_APP_OFFSET,
+      csr_resets_global_o => csr_rst_gbl,
+      csr_resets_appl_o   => csr_rst_app,
+
+      -- presence lines for the fmcs
+      csr_fmc_presence_i  => fmc_presence,
+
+      csr_ddr_status_ddr4_calib_done_i    => ddr_init_done,
+      csr_ddr_status_ddr5_calib_done_i    => '1',
+      csr_pcb_rev_rev_i   => pcbrev_i,
+
+
+      csr_ddr4_addr_i => (others => '0'),
+      csr_ddr4_data_i => (others => '0'),
+      csr_ddr4_data_wack_i => '0',
+      csr_ddr4_data_rack_i => '0',
+      
+--      csr_ddr4_addr_i      => csr_ddr4_addr,
+  --    csr_ddr4_addr_o      => csr_ddr4_addr_out,
+    --  csr_ddr4_addr_wr_o   => csr_ddr4_addr_wr,
+  --
+      -- data to read or to write in ddr4
+     -- csr_ddr4_data_i      => csr_ddr4_data_in,
+     -- csr_ddr4_data_o      => csr_ddr4_data_out,
+     -- csr_ddr4_data_wr_o   => csr_ddr4_data_wr,
+     -- csr_ddr4_data_rd_o   => csr_ddr4_data_rd,
+     -- csr_ddr4_data_wack_i => csr_ddr4_data_wack,
+     -- csr_ddr4_data_rack_i => csr_ddr4_data_rack,
+  
+      -- Thermometer and unique id
+      therm_id_i          => therm_id_in,
+      therm_id_o          => therm_id_out,
+
+      -- i2c controllers to the fmcs
+      fmc_i2c_i           => fmc_i2c_in,
+      fmc_i2c_o           => fmc_i2c_out,
+
+      -- spi controller to the flash
+      flash_spi_i         => flash_spi_in,
+      flash_spi_o         => flash_spi_out,
+
+      -- vector interrupt controller
+      vic_i               => vic_in,
+      vic_o               => vic_out,
+
+      -- a ROM containing build info
+      buildinfo_addr_o => buildinfo_addr,
+      buildinfo_data_i => buildinfo_data,
+      buildinfo_data_o => open,
+
+      -- white-rabbit core
+      wrc_regs_i          => wrc_in,
+      wrc_regs_o          => wrc_out
+    );
+
+  fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
+  fmc_presence (1) <= not fmc1_prsnt_m2c_n_i;
+  fmc_presence (31 downto 2) <= (others => '0');
+
+  --  Metadata
+  p_metadata: process (clk_sys_62m5) is
+  begin
+    if rising_edge(clk_sys_62m5) then
+      case metadata_addr is
+        when x"0" =>
+          -- Vendor ID
+          metadata_data <= x"000010dc";
+        when x"1" =>
+          -- Device ID
+          metadata_data <= x"53564543";
+        when x"2" =>
+          -- Version
+          metadata_data <= x"01040000";
+        when x"3" =>
+          -- BOM
+          metadata_data <= x"fffe0000";
+        when x"4" | x"5" | x"6" | x"7" =>
+          -- source id
+          metadata_data <= x"00000000";
+        when x"8" =>
+          -- capability mask
+          metadata_data <= x"00000000";
+          if g_WITH_VIC then
+            metadata_data(0) <= '1';
+          end if;
+          if g_WITH_ONEWIRE and not g_WITH_WR then
+            metadata_data(1) <= '1';
+          end if;
+          if g_WITH_SPI then
+            metadata_data(2) <= '1';
+          end if;
+          if g_WITH_WR then
+            metadata_data(3) <= '1';
+          end if;
+          --  Buildinfo
+          metadata_data(4) <= '1';
+          if g_WITH_DDR then
+            metadata_data(5) <= '1';
+          end if;
+          if g_WITH_DDR then
+            metadata_data(6) <= '1';
+          end if;
+        when others =>
+          metadata_data <= x"00000000";
+      end case;
+    end if;
+  end process;
+
+  --  Build information
+  p_buildinfo: process (clk_sys_62m5) is
+    variable addr : natural;
+    variable b : std_logic_vector(7 downto 0);
+  begin
+    if rising_edge(clk_sys_62m5) then
+      addr := to_integer(unsigned(buildinfo_addr)) * 4;
+      for i in 0 to 3 loop
+        if addr + i < buildinfo'length then
+           b := std_logic_vector(to_unsigned(character'pos(
+             buildinfo(buildinfo'left + addr + i)), 8));
+        else
+           b := x"00";
+        end if;
+        buildinfo_data (7 + i * 8 downto i * 8) <= b;
+      end loop;
+    end if;
+  end process;
+
+  rst_gbl_n <= rst_sys_62m5_n and (not csr_rst_gbl);
+
+  -- reset for DDR including soft reset.
+  -- This is treated as async and will be re-synced by the DDR controller
+  ddr_rst <= csr_rst_gbl;
+
+  rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
+
+  rst_sys_62m5_n_o <= rst_sys_62m5_n and rst_csr_app_n;
+  clk_sys_62m5_o <= clk_sys_62m5;
+
+  i_rst_csr_app_sync : gc_sync_ffs
+    port map (
+      clk_i    => clk_ref_62m5,
+      rst_n_i  => '1',
+      data_i   => rst_csr_app_n,
+      synced_o => rst_csr_app_sync_n);
+
+  rst_ref_62m5_n_o <= rst_ref_62m5_n and rst_csr_app_sync_n;
+  clk_ref_62m5_o   <= clk_ref_62m5;
+
+  inst_i2c: entity work.xwb_i2c_master
+    generic map (
+      g_interface_mode      => CLASSIC,
+      g_address_granularity => BYTE,
+      g_num_interfaces      => 2)
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i   => rst_gbl_n,
+
+      slave_i => fmc_i2c_out,
+      slave_o => fmc_i2c_in,
+      desc_o  => open,
+
+      int_o   => irqs(0),
+
+      scl_pad_i (0)    => fmc0_scl_b,
+      scl_pad_i (1)    => fmc1_scl_b,
+      scl_pad_o (0)    => fmc0_scl_out,
+      scl_pad_o (1)    => fmc1_scl_out,
+      scl_padoen_o (0) => fmc0_scl_oen,
+      scl_padoen_o (1) => fmc1_scl_oen,
+      sda_pad_i (0)    => fmc0_sda_b,
+      sda_pad_i (1)    => fmc1_sda_b,
+      sda_pad_o (0)    => fmc0_sda_out,
+      sda_pad_o (1)    => fmc1_sda_out,
+      sda_padoen_o (0) => fmc0_sda_oen,
+      sda_padoen_o (1) => fmc1_sda_oen
+    );
+
+  fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oen = '0' else 'Z';
+  fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oen = '0' else 'Z';
+
+  fmc1_scl_b <= fmc1_scl_out when fmc1_scl_oen = '0' else 'Z';
+  fmc1_sda_b <= fmc1_sda_out when fmc1_sda_oen = '0' else 'Z';
+
+  gen_user_irq: if g_NUM_USER_IRQ > 0 generate
+    irqs(irq_user_i'range) <= irq_user_i;
+  end generate gen_user_irq;
+
+  gen_vic: if g_with_vic generate
+    i_vic: entity work.xwb_vic
+      generic map (
+        g_address_granularity => BYTE,
+        g_num_interrupts => num_interrupts
+      )
+      port map (
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i => rst_gbl_n,
+        slave_i => vic_out,
+        slave_o => vic_in,
+        irqs_i => irqs,
+        irq_master_o => irq_master
+      );
+  end generate;
+
+  gen_no_vic: if not g_with_vic generate
+    vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
+    irq_master <= '0';
+  end generate;
+
+  irqs(4) <= '0';
+  irqs(5) <= '0';
+
+  -----------------------------------------------------------------------------
+  -- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
+  -----------------------------------------------------------------------------
+
+  gen_wr: if g_WITH_WR generate
+    -- OneWire
+    signal onewire_data : std_logic;
+    signal onewire_oe   : std_logic;
+  begin
+    --  Remap WR registers.
+    wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
+                   adr => wrc_out.adr or x"00020000",
+                   sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
+
+    cmp_xwrc_board_svec : entity work.xwrc_board_svec7
+      generic map (
+        g_simulation                => g_SIMULATION,
+        g_VERBOSE                   => g_VERBOSE,
+        g_with_external_clock_input => TRUE,
+        g_dpram_initf               => g_DPRAM_INITF,
+        g_AUX_CLKS                  => g_AUX_CLKS,
+        g_AUX_PLL_CFG               => c_WRPC_PLL_CONFIG,
+        g_STREAMERS_OP_MODE         => g_STREAMERS_OP_MODE,
+        g_TX_STREAMER_PARAMS        => g_TX_STREAMER_PARAMS,
+        g_RX_STREAMER_PARAMS        => g_RX_STREAMER_PARAMS,
+        g_FABRIC_IFACE              => g_FABRIC_IFACE)
+      port map (
+        areset_n_i          => rst_n_i,
+        clk_20m_vcxo_i      => clk_20m_vcxo_i,
+        clk_62m5_pllref_p_i => clk_62m5_pllref_p_i,
+        clk_62m5_pllref_n_i => clk_62m5_pllref_n_i,
+        clk_125m_gtx_n_i    => clk_125m_gtx_n_i,
+        clk_125m_gtx_p_i    => clk_125m_gtx_p_i,
+        clk_aux_i           => clk_aux_i,
+        clk_10m_ext_i       => clk_10m_ext_i,
+        pps_ext_i           => pps_ext_i,
+
+        clk_sys_62m5_o      => clk_sys_62m5,
+        clk_ref_62m5_o      => clk_ref_62m5,
+        clk_pll_aux_o       => clk_pll_aux,
+        clk_dmtd_62m5_o     => clk_dmtd_62m5,
+        rst_sys_62m5_n_o    => rst_sys_62m5_n,
+        rst_ref_62m5_n_o    => rst_ref_62m5_n,
+        rst_pll_aux_n_o     => rst_pll_aux_n,
+
+        pll20dac_din_o      => pll20dac_din_o,
+        pll20dac_sclk_o     => pll20dac_sclk_o,
+        pll20dac_sync_n_o   => pll20dac_sync_n_o,
+        pll25dac_din_o      => pll25dac_din_o,
+        pll25dac_sclk_o     => pll25dac_sclk_o,
+        pll25dac_sync_n_o   => pll25dac_sync_n_o,
+
+        sfp_txp_o           => sfp_txp_o,
+        sfp_txn_o           => sfp_txn_o,
+        sfp_rxp_i           => sfp_rxp_i,
+        sfp_rxn_i           => sfp_rxn_i,
+        sfp_det_i           => sfp_mod_def0_i,
+        sfp_sda_i           => sfp_sda_in,
+        sfp_sda_o           => sfp_sda_out,
+        sfp_scl_i           => sfp_scl_in,
+        sfp_scl_o           => sfp_scl_out,
+        sfp_rate_select_o   => sfp_rate_select_o,
+        sfp_tx_fault_i      => sfp_tx_fault_i,
+        sfp_tx_disable_o    => sfp_tx_disable_o,
+        sfp_los_i           => sfp_los_i,
+
+        eeprom_sda_i        => eeprom_sda_in,
+        eeprom_sda_o        => eeprom_sda_out,
+        eeprom_scl_i        => eeprom_scl_in,
+        eeprom_scl_o        => eeprom_scl_out,
+
+        onewire_i           => onewire_data,
+        onewire_oen_o       => onewire_oe,
+        -- Uart
+        uart_rxd_i          => uart_rxd_i,
+        uart_txd_o          => uart_txd_o,
+        -- SPI Flash (not used)
+        spi_ncs_o           => open,
+        spi_mosi_o          => open,
+        spi_miso_i          => '0',
+
+        wb_slave_o          => wrc_in,
+        wb_slave_i          => wrc_out_sh,
+
+        wrf_src_o           => wrf_src_o,
+        wrf_src_i           => wrf_src_i,
+        wrf_snk_o           => wrf_snk_o,
+        wrf_snk_i           => wrf_snk_i,
+        wrs_tx_data_i       => wrs_tx_data_i,
+        wrs_tx_valid_i      => wrs_tx_valid_i,
+        wrs_tx_dreq_o       => wrs_tx_dreq_o,
+        wrs_tx_last_i       => wrs_tx_last_i,
+        wrs_tx_flush_i      => wrs_tx_flush_i,
+        wrs_tx_cfg_i        => wrs_tx_cfg_i,
+        wrs_rx_first_o      => wrs_rx_first_o,
+        wrs_rx_last_o       => wrs_rx_last_o,
+        wrs_rx_data_o       => wrs_rx_data_o,
+        wrs_rx_valid_o      => wrs_rx_valid_o,
+        wrs_rx_dreq_i       => wrs_rx_dreq_i,
+        wrs_rx_cfg_i        => wrs_rx_cfg_i,
+        wb_eth_master_o     => wb_eth_master_o,
+        wb_eth_master_i     => wb_eth_master_i,
+
+        tm_link_up_o        => tm_link_up_o,
+        tm_time_valid_o     => tm_time_valid_o,
+        tm_tai_o            => tm_tai_o,
+        tm_cycles_o         => tm_cycles_o,
+
+        tm_dac_value_o       => tm_dac_value_o,
+        tm_dac_wr_o          => tm_dac_wr_o,
+        tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
+        tm_clk_aux_locked_o  => tm_clk_aux_locked_o,
+
+        pps_p_o             => pps_p_o,
+        pps_led_o           => pps_led_o,
+        link_ok_o           => link_ok_o,
+        led_link_o          => led_link_o,
+        led_act_o           => led_act_o);
+
+
+    -- Tristates for SFP EEPROM
+    sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
+    sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
+    sfp_scl_in     <= sfp_mod_def1_b;
+    sfp_sda_in     <= sfp_mod_def2_b;
+
+    -- Tristates for Carrier EEPROM
+    carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
+    carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
+    eeprom_scl_in <= carrier_scl_b;
+    eeprom_sda_in <= carrier_sda_b;
+
+    -- tri-state onewire access
+    onewire_b    <= '0' when (onewire_oe = '1') else 'Z';
+    onewire_data <= onewire_b;
+
+    --  WR means neither onewire nor spi.
+    assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
+      severity failure;
+    therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
+      dat => (others => '0'));
+  end generate;
+
+  gen_no_wr: if not g_WITH_WR generate
+    signal clk_62m5_pllref : std_logic;
+    signal pllout_clk_fb_pllref : std_logic;
+    signal pllout_clk_sys_62m5 : std_logic;
+    signal pllout_clk_ref_62m5 : std_logic;
+    signal pllout_locked : std_logic;
+    signal rstlogic_arst : std_logic;
+  begin
+    -- Input clock
+    cmp_pllrefclk_buf : IBUFGDS
+      generic map (
+        DIFF_TERM    => true,             -- Differential Termination
+        IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O  => clk_62m5_pllref,            -- Buffer output
+        I  => clk_62m5_pllref_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+        IB => clk_62m5_pllref_n_i  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+    -- fixme: port to kintex7
+    
+    -- cmp_sys_clk_pll : PLLE2_ADV
+    --   generic map (
+    --     BANDWIDTH          => "OPTIMIZED",
+    --     CLK_FEEDBACK       => "CLKFBOUT",
+    --     COMPENSATION       => "INTERNAL",
+    --     DIVCLK_DIVIDE      => 1,
+    --     CLKFBOUT_MULT      => 16,
+    --     CLKFBOUT_PHASE     => 0.000,
+    --     CLKOUT0_DIVIDE     => 16,        -- 62.5 MHz
+    --     CLKOUT0_PHASE      => 0.000,
+    --     CLKOUT0_DUTY_CYCLE => 0.500,
+    --     CLKOUT1_DIVIDE     => 16,         -- 125 MHz
+    --     CLKOUT1_PHASE      => 0.000,
+    --     CLKOUT1_DUTY_CYCLE => 0.500,
+    --     CLKOUT2_DIVIDE     => 3,         -- 333 MHz
+    --     CLKOUT2_PHASE      => 0.000,
+    --     CLKOUT2_DUTY_CYCLE => 0.500,
+    --     CLKIN_PERIOD       => 8.0,
+    --     REF_JITTER         => 0.016)
+    --   port map (
+    --     CLKFBOUT => pllout_clk_fb_pllref,
+    --     CLKOUT0  => pllout_clk_sys_62m5,
+    --     CLKOUT1  => pllout_clk_ref_62m5,
+    --     CLKOUT2  => open,
+    --     CLKOUT3  => open,
+    --     CLKOUT4  => open,
+    --     CLKOUT5  => open,
+    --     LOCKED   => pllout_locked,
+    --     RST      => '0',
+    --     CLKFBIN  => pllout_clk_fb_pllref,
+    --     CLKIN    => clk_62m5_pllref);
+
+    cmp_clk_62m5_buf : BUFG
+      port map (
+        O => clk_sys_62m5,
+        I => pllout_clk_sys_62m5);
+
+    cmp_clk_125m_buf : BUFG
+      port map (
+        O => clk_ref_62m5,
+        I => pllout_clk_ref_62m5);
+
+
+    -- logic AND of all async reset sources (active high)
+    rstlogic_arst <= (not pllout_locked) and (not rst_n_i);
+
+    -- Clocks required to have synced resets
+    cmp_rstlogic_reset : gc_reset_multi_aasd
+      generic map (
+        g_CLOCKS  => 2,
+        g_RST_LEN => 16)  -- 16 clock cycles
+      port map (
+        arst_i  => rstlogic_arst,
+        clks_i (0)  => clk_sys_62m5,
+        clks_i (1)  => clk_ref_62m5,
+        rst_n_o (0) => rst_sys_62m5_n,
+        rst_n_o (1) => rst_ref_62m5_n);
+
+    --  Not used.
+    wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
+  end generate;
+
+  gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
+    i_onewire: entity work.xwb_ds182x_readout
+      generic map (
+        g_CLOCK_FREQ_KHZ => 62_500,
+        g_USE_INTERNAL_PPS => True)
+      port map (
+        clk_i => clk_sys_62m5,
+        rst_n_i => rst_gbl_n,
+
+        wb_i => therm_id_out,
+        wb_o => therm_id_in,
+
+        pps_p_i => '0',
+        onewire_b => onewire_b
+      );
+  end generate;
+
+  gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
+    therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
+    onewire_b <= 'Z';
+  end generate;
+
+  gen_spi: if g_WITH_SPI generate
+    signal spi_sclk : std_logic;
+  begin
+    
+    i_spi: entity work.xwb_spi
+      generic map (
+        g_interface_mode => CLASSIC,
+        g_address_granularity => BYTE,
+        g_divider_len => open,
+        g_max_char_len => open,
+        g_num_slaves => 1
+      )
+      port map (
+        clk_sys_i => clk_sys_62m5,
+        rst_n_i => rst_gbl_n,
+        slave_i => flash_spi_out,
+        slave_o => flash_spi_in,
+        desc_o => open,
+        int_o => irqs(1),
+        pad_cs_o(0) => spi_ncs_o,
+        pad_sclk_o => spi_sclk,
+        pad_mosi_o => spi_mosi_o,
+        pad_miso_i => spi_miso_i
+        );
+
+  U_Kintex7_Startup : STARTUPE2
+    generic map (
+      PROG_USR      => "FALSE",
+      SIM_CCLK_FREQ => 0.0)
+    port map (
+      CFGCLK    => open,
+      CFGMCLK   => open,
+      EOS       => open,
+      PREQ      => open,
+      CLK => '0',
+      GSR       => '0',
+      GTS       => '0',
+      KEYCLEARB => '1',
+      PACK      => '1',
+      USRCCLKO  => spi_sclk,
+      USRCCLKTS => '0', -- always out
+      USRDONEO  => '1',
+      USRDONETS => '1');
+
+    
+  end generate;
+
+  gen_no_spi : if not g_WITH_SPI generate
+    flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
+    irqs(1)      <= '0';
+    spi_ncs_o    <= '1';
+    spi_mosi_o   <= '0';
+  end generate;
+
+  --  DDR3 controller
+  gen_with_ddr: if g_WITH_DDR generate
+    signal pllout_ddr_clk_fb : std_logic;
+    signal pllout_ddr_clk_fb_bufg : std_logic;
+    signal pllout_clk_ddr_iodelay : std_logic;
+    signal pllout_ddr_locked : std_logic;
+    signal clk_ddr_sys4x : std_logic;
+    signal clk_ddr_sys4x_dqs : std_logic;
+    signal clk_ddr_iodelay : std_logic;
+  begin
+    
+    cmp_ddr_clk_pll : PLLE2_ADV
+      generic map (
+      BANDWIDTH          => ("HIGH"),
+      COMPENSATION       => ("ZHOLD"),
+      STARTUP_WAIT       => ("FALSE"),
+
+        DIVCLK_DIVIDE      => 1,
+        CLKFBOUT_MULT      => 16,
+        CLKFBOUT_PHASE     => 0.000,
+        CLKOUT0_DIVIDE     => 2,        -- 500 MHz
+        CLKOUT0_PHASE      => 0.000,
+        CLKOUT0_DUTY_CYCLE => 0.500,
+        CLKOUT1_DIVIDE     => 2,        -- 500 MHz / 90 deg
+        CLKOUT1_PHASE      => 90.000,
+        CLKOUT1_DUTY_CYCLE => 0.500,
+        CLKOUT2_DIVIDE     => 5,        -- 200 MHz
+        CLKOUT2_PHASE      => 0.000,
+        CLKOUT2_DUTY_CYCLE => 0.500,
+        CLKIN1_PERIOD       => 16.0 )
+      port map (
+        CLKFBOUT => pllout_ddr_clk_fb,
+        CLKOUT0  => clk_ddr_sys4x,
+        CLKOUT1  => clk_ddr_sys4x_dqs,
+        CLKOUT2 => pllout_clk_ddr_iodelay,
+        LOCKED   => pllout_ddr_locked,
+        RST      => '0',
+        CLKFBIN  => pllout_ddr_clk_fb_bufg,
+        CLKIN1    => ddr_clk_i,
+        CLKIN2    => '0',
+        CLKINSEL => '1',
+        DADDR => (others => '0'),
+        dwe => '0',
+        di => (others => '0'),
+        dclk => '0',
+        den => '0',
+        PWRDWN => '0'
+        );
+
+    cmp_clk_ddr_iodelay : BUFG
+      port map (
+        O => clk_ddr_iodelay,
+        I => pllout_clk_ddr_iodelay);
+
+    cmp_clk_ddr_fb : BUFG
+      port map (
+        O => pllout_ddr_clk_fb_bufg,
+        I => pllout_ddr_clk_fb);
+
+    cmp_ddr_idelayctrl : IDELAYCTRL
+    port map (
+      RDY    => open,                   
+      REFCLK => clk_ddr_iodelay,      
+      RST    => '0'                   
+      );
+    
+    cmp_litedram_ctrl : entity work.litedram_core
+      port map (
+--	serial_tx => open, --litedram_serial_tx,
+--	serial_rx => '1', --litedram_serial_rx,
+	rst => ddr_rst,
+	clk_sys => ddr_clk_i,
+        clk_sys_4x => clk_ddr_sys4x,
+        clk_sys_4x_dqs => clk_ddr_sys4x_dqs,
+	ddram_a => ddr_a_o,
+	ddram_ba => ddr_ba_o,
+	ddram_ras_n => ddr_ras_n_o,
+	ddram_cas_n => ddr_cas_n_o,
+	ddram_we_n => ddr_we_n_o,
+	ddram_cs_n => ddr_cs_n_o,
+	ddram_dm => ddr_dm_o,
+	ddram_dq => ddr_dq_b,
+	ddram_dqs_p => ddr_dqs_p_b,
+	ddram_dqs_n => ddr_dqs_n_b,
+	ddram_clk_p => ddr_ck_p_o,
+	ddram_clk_n => ddr_ck_n_o,
+	ddram_cke => ddr_cke_o,
+	ddram_odt => ddr_odt_o,
+	ddram_reset_n => ddr_reset_n_o,
+	init_done  => open,
+	init_error => open,
+
+        user_port0_aw_valid => ddr_axi4_i.AWVALID,
+        user_port0_aw_ready => ddr_axi4_o.AWREADY,
+        user_port0_aw_addr=> ddr_axi4_i.AWADDR,
+        user_port0_aw_burst=> ddr_axi4_i.AWBURST,
+        user_port0_aw_len=> ddr_axi4_i.AWLEN,
+        user_port0_aw_size=> ddr_axi4_i.AWSIZE,
+        user_port0_aw_id=> ddr_axi4_i.AWID,
+        user_port0_w_valid => ddr_axi4_i.WVALID,
+        user_port0_w_ready=> ddr_axi4_o.WREADY,
+        user_port0_w_last=> ddr_axi4_i.WLAST,
+        user_port0_w_strb=> ddr_axi4_i.WSTRB,
+	user_port0_w_data=> ddr_axi4_i.WDATA,
+	user_port0_b_valid=> ddr_axi4_o.BVALID,
+	user_port0_b_ready=> ddr_axi4_i.BREADY,
+        user_port0_b_resp=> ddr_axi4_o.BRESP,
+        user_port0_b_id=> ddr_axi4_o.BID,
+	user_port0_ar_valid=> ddr_axi4_i.ARVALID,
+	user_port0_ar_ready=> ddr_axi4_o.ARREADY,
+	user_port0_ar_addr=> ddr_axi4_i.ARADDR,
+	user_port0_ar_burst=> ddr_axi4_i.ARBURST,
+	user_port0_ar_len=> ddr_axi4_i.ARLEN,
+	user_port0_ar_size=> ddr_axi4_i.ARSIZE,
+	user_port0_ar_id=> ddr_axi4_i.ARID,
+	user_port0_r_valid=> ddr_axi4_o.RVALID,
+	user_port0_r_ready=> ddr_axi4_i.RREADY,
+	user_port0_r_last=> ddr_axi4_o.RLAST,
+	user_port0_r_resp=> ddr_axi4_o.RRESP,
+	user_port0_r_data=> ddr_axi4_o.RDATA,
+	user_port0_r_id=> ddr_axi4_o.RID);
+
+  
+  end generate gen_with_ddr;
+
+  gen_without_ddr : if not g_WITH_DDR generate
+    ddr_a_o             <= (others => '0');
+    ddr_ba_o            <= (others => '0');
+    ddr_dq_b            <= (others => 'Z');
+    ddr_cas_n_o         <= '0';
+    ddr_ck_p_o          <= '0';
+    ddr_ck_n_o          <= '0';
+    ddr_cke_o           <= '0';
+    ddr_odt_o           <= '0';
+    ddr_dm_o           <= (others => '0');
+    ddr_ras_n_o         <= '0';
+    ddr_reset_n_o       <= '0';
+    ddr_we_n_o          <= '0';
+    ddr_cs_n_o <= '1';
+    ddr_rzq_b           <= 'Z';
+  end generate gen_without_ddr;
+
+
+  clk_dmtd_62m5_o <= clk_dmtd_62m5;
+end architecture top;
--- a/hdl/syn/svec7_test/Manifest.py
+++ b/hdl/syn/svec7_test/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7k325t"
+syn_grade = "-2"
+syn_package = "ffg900"
+
+syn_top = "svec7_test_top"
+syn_project = "svec7_test_top"
+
+syn_tool = "vivado"
+
+include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm", 
+               "../../../../general-cores/sim",
+		"../../../../general-cores/modules/wishbone/wb_spi",
+		"../../../../general-cores/modules/wishbone/wb_lm32/src",
+	       "." ]
+
+modules = {
+  "local" :  [ "../../rtl/svec7",
+	"../../top/svec7_test",
+      "../../../../wr-cores",
+      "../../../../general-cores",
+      "../../../../vme64x-core"
+      
+  ],
+}
--- a/hdl/syn/svec7_test/pins.xdc
+++ b/hdl/syn/svec7_test/pins.xdc
+set_property PACKAGE_PIN AG29 [get_ports {clk_20m_vcxo_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {clk_20m_vcxo_i}]
+set_property PACKAGE_PIN AD23 [get_ports {clk_62m5_pllref_p_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_62m5_pllref_p_i}]
+set_property PACKAGE_PIN AE24 [get_ports {clk_62m5_pllref_n_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_62m5_pllref_n_i}]
+set_property PACKAGE_PIN R7 [get_ports {clk_125m_gtx_n_i}]
+set_property PACKAGE_PIN R8 [get_ports {clk_125m_gtx_p_i}]
+set_property PACKAGE_PIN AF22 [get_ports {clk_fpga2_p_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_fpga2_p_i}]
+set_property PACKAGE_PIN AG23 [get_ports {clk_fpga2_n_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_fpga2_n_i}]
+set_property PACKAGE_PIN AB27 [get_ports {clk_si57x_p_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_si57x_p_i}]
+set_property PACKAGE_PIN AC27 [get_ports {clk_si57x_n_i}]
+set_property IOSTANDARD LVDS [get_ports {clk_si57x_n_i}]
+set_property PACKAGE_PIN L25 [get_ports {fmc0_clk_m2c_p_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[0]}]
+set_property PACKAGE_PIN K25 [get_ports {fmc0_clk_m2c_n_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[0]}]
+set_property PACKAGE_PIN K28 [get_ports {fmc0_clk_m2c_p_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[1]}]
+set_property PACKAGE_PIN K29 [get_ports {fmc0_clk_m2c_n_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[1]}]
+set_property PACKAGE_PIN C25 [get_ports {fmc1_clk_m2c_p_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[0]}]
+set_property PACKAGE_PIN B25 [get_ports {fmc1_clk_m2c_n_i[0]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[0]}]
+set_property PACKAGE_PIN D27 [get_ports {fmc1_clk_m2c_p_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[1]}]
+set_property PACKAGE_PIN D27 [get_ports {fmc1_clk_m2c_n_i[1]}]
+set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[1]}]
+set_property PACKAGE_PIN P24 [get_ports {fmc0_la_p_b[0]}]
+set_property PACKAGE_PIN R20 [get_ports {fmc0_la_p_b[1]}]
+set_property PACKAGE_PIN R23 [get_ports {fmc0_la_p_b[2]}]
+set_property PACKAGE_PIN T20 [get_ports {fmc0_la_p_b[3]}]
+set_property PACKAGE_PIN T22 [get_ports {fmc0_la_p_b[4]}]
+set_property PACKAGE_PIN U19 [get_ports {fmc0_la_p_b[5]}]
+set_property PACKAGE_PIN P29 [get_ports {fmc0_la_p_b[6]}]
+set_property PACKAGE_PIN P27 [get_ports {fmc0_la_p_b[7]}]
+set_property PACKAGE_PIN R30 [get_ports {fmc0_la_p_b[8]}]
+set_property PACKAGE_PIN P26 [get_ports {fmc0_la_p_b[9]}]
+set_property PACKAGE_PIN R28 [get_ports {fmc0_la_p_b[10]}]
+set_property PACKAGE_PIN T26 [get_ports {fmc0_la_p_b[11]}]
+set_property PACKAGE_PIN U27 [get_ports {fmc0_la_p_b[12]}]
+set_property PACKAGE_PIN T25 [get_ports {fmc0_la_p_b[13]}]
+set_property PACKAGE_PIN U29 [get_ports {fmc0_la_p_b[14]}]
+set_property PACKAGE_PIN V26 [get_ports {fmc0_la_p_b[15]}]
+set_property PACKAGE_PIN V29 [get_ports {fmc0_la_p_b[16]}]
+set_property PACKAGE_PIN V25 [get_ports {fmc0_la_p_b[17]}]
+set_property PACKAGE_PIN V19 [get_ports {fmc0_la_p_b[18]}]
+set_property PACKAGE_PIN W23 [get_ports {fmc0_la_p_b[19]}]
+set_property PACKAGE_PIN U22 [get_ports {fmc0_la_p_b[20]}]
+set_property PACKAGE_PIN V21 [get_ports {fmc0_la_p_b[21]}]
+set_property PACKAGE_PIN U24 [get_ports {fmc0_la_p_b[22]}]
+set_property PACKAGE_PIN W21 [get_ports {fmc0_la_p_b[23]}]
+set_property PACKAGE_PIN J23 [get_ports {fmc0_la_p_b[24]}]
+set_property PACKAGE_PIN L22 [get_ports {fmc0_la_p_b[25]}]
+set_property PACKAGE_PIN K23 [get_ports {fmc0_la_p_b[26]}]
+set_property PACKAGE_PIN L21 [get_ports {fmc0_la_p_b[27]}]
+set_property PACKAGE_PIN J21 [get_ports {fmc0_la_p_b[28]}]
+set_property PACKAGE_PIN M20 [get_ports {fmc0_la_p_b[29]}]
+set_property PACKAGE_PIN J29 [get_ports {fmc0_la_p_b[30]}]
+set_property PACKAGE_PIN J27 [get_ports {fmc0_la_p_b[31]}]
+set_property PACKAGE_PIN L30 [get_ports {fmc0_la_p_b[32]}]
+set_property PACKAGE_PIN K26 [get_ports {fmc0_la_p_b[33]}]
+set_property PACKAGE_PIN R25 [get_ports {fmc0_la_n_b[0]}]
+set_property PACKAGE_PIN R21 [get_ports {fmc0_la_n_b[1]}]
+set_property PACKAGE_PIN R24 [get_ports {fmc0_la_n_b[2]}]
+set_property PACKAGE_PIN T21 [get_ports {fmc0_la_n_b[3]}]
+set_property PACKAGE_PIN T23 [get_ports {fmc0_la_n_b[4]}]
+set_property PACKAGE_PIN U20 [get_ports {fmc0_la_n_b[5]}]
+set_property PACKAGE_PIN R29 [get_ports {fmc0_la_n_b[6]}]
+set_property PACKAGE_PIN P28 [get_ports {fmc0_la_n_b[7]}]
+set_property PACKAGE_PIN T30 [get_ports {fmc0_la_n_b[8]}]
+set_property PACKAGE_PIN R26 [get_ports {fmc0_la_n_b[9]}]
+set_property PACKAGE_PIN T28 [get_ports {fmc0_la_n_b[10]}]
+set_property PACKAGE_PIN T27 [get_ports {fmc0_la_n_b[11]}]
+set_property PACKAGE_PIN U28 [get_ports {fmc0_la_n_b[12]}]
+set_property PACKAGE_PIN U25 [get_ports {fmc0_la_n_b[13]}]
+set_property PACKAGE_PIN U30 [get_ports {fmc0_la_n_b[14]}]
+set_property PACKAGE_PIN V27 [get_ports {fmc0_la_n_b[15]}]
+set_property PACKAGE_PIN V30 [get_ports {fmc0_la_n_b[16]}]
+set_property PACKAGE_PIN W26 [get_ports {fmc0_la_n_b[17]}]
+set_property PACKAGE_PIN V20 [get_ports {fmc0_la_n_b[18]}]
+set_property PACKAGE_PIN W24 [get_ports {fmc0_la_n_b[19]}]
+set_property PACKAGE_PIN U23 [get_ports {fmc0_la_n_b[20]}]
+set_property PACKAGE_PIN V22 [get_ports {fmc0_la_n_b[21]}]
+set_property PACKAGE_PIN V24 [get_ports {fmc0_la_n_b[22]}]
+set_property PACKAGE_PIN W22 [get_ports {fmc0_la_n_b[23]}]
+set_property PACKAGE_PIN J24 [get_ports {fmc0_la_n_b[24]}]
+set_property PACKAGE_PIN L23 [get_ports {fmc0_la_n_b[25]}]
+set_property PACKAGE_PIN K24 [get_ports {fmc0_la_n_b[26]}]
+set_property PACKAGE_PIN K21 [get_ports {fmc0_la_n_b[27]}]
+set_property PACKAGE_PIN J22 [get_ports {fmc0_la_n_b[28]}]
+set_property PACKAGE_PIN L20 [get_ports {fmc0_la_n_b[29]}]
+set_property PACKAGE_PIN H29 [get_ports {fmc0_la_n_b[30]}]
+set_property PACKAGE_PIN J28 [get_ports {fmc0_la_n_b[31]}]
+set_property PACKAGE_PIN K30 [get_ports {fmc0_la_n_b[32]}]
+set_property PACKAGE_PIN J26 [get_ports {fmc0_la_n_b[33]}]
+set_property PACKAGE_PIN L26 [get_ports {fmc1_la_p_b[0]}]
+set_property PACKAGE_PIN L25 [get_ports {fmc1_la_p_b[1]}]
+set_property PACKAGE_PIN K28 [get_ports {fmc1_la_p_b[2]}]
+set_property PACKAGE_PIN M28 [get_ports {fmc1_la_p_b[3]}]
+set_property PACKAGE_PIN M29 [get_ports {fmc1_la_p_b[4]}]
+set_property PACKAGE_PIN N27 [get_ports {fmc1_la_p_b[5]}]
+set_property PACKAGE_PIN N29 [get_ports {fmc1_la_p_b[6]}]
+set_property PACKAGE_PIN N25 [get_ports {fmc1_la_p_b[7]}]
+set_property PACKAGE_PIN N19 [get_ports {fmc1_la_p_b[8]}]
+set_property PACKAGE_PIN N21 [get_ports {fmc1_la_p_b[9]}]
+set_property PACKAGE_PIN P23 [get_ports {fmc1_la_p_b[10]}]
+set_property PACKAGE_PIN P21 [get_ports {fmc1_la_p_b[11]}]
+set_property PACKAGE_PIN M24 [get_ports {fmc1_la_p_b[12]}]
+set_property PACKAGE_PIN M22 [get_ports {fmc1_la_p_b[13]}]
+set_property PACKAGE_PIN B23 [get_ports {fmc1_la_p_b[14]}]
+set_property PACKAGE_PIN E23 [get_ports {fmc1_la_p_b[15]}]
+set_property PACKAGE_PIN F25 [get_ports {fmc1_la_p_b[16]}]
+set_property PACKAGE_PIN E24 [get_ports {fmc1_la_p_b[17]}]
+set_property PACKAGE_PIN F26 [get_ports {fmc1_la_p_b[18]}]
+set_property PACKAGE_PIN G23 [get_ports {fmc1_la_p_b[19]}]
+set_property PACKAGE_PIN B27 [get_ports {fmc1_la_p_b[20]}]
+set_property PACKAGE_PIN C24 [get_ports {fmc1_la_p_b[21]}]
+set_property PACKAGE_PIN B28 [get_ports {fmc1_la_p_b[22]}]
+set_property PACKAGE_PIN A25 [get_ports {fmc1_la_p_b[23]}]
+set_property PACKAGE_PIN D26 [get_ports {fmc1_la_p_b[24]}]
+set_property PACKAGE_PIN C25 [get_ports {fmc1_la_p_b[25]}]
+set_property PACKAGE_PIN D27 [get_ports {fmc1_la_p_b[26]}]
+set_property PACKAGE_PIN E28 [get_ports {fmc1_la_p_b[27]}]
+set_property PACKAGE_PIN C29 [get_ports {fmc1_la_p_b[28]}]
+set_property PACKAGE_PIN D29 [get_ports {fmc1_la_p_b[29]}]
+set_property PACKAGE_PIN B30 [get_ports {fmc1_la_p_b[30]}]
+set_property PACKAGE_PIN E29 [get_ports {fmc1_la_p_b[31]}]
+set_property PACKAGE_PIN H24 [get_ports {fmc1_la_p_b[32]}]
+set_property PACKAGE_PIN G28 [get_ports {fmc1_la_p_b[33]}]
+set_property PACKAGE_PIN L27 [get_ports {fmc1_la_n_b[0]}]
+set_property PACKAGE_PIN K25 [get_ports {fmc1_la_n_b[1]}]
+set_property PACKAGE_PIN K29 [get_ports {fmc1_la_n_b[2]}]
+set_property PACKAGE_PIN L28 [get_ports {fmc1_la_n_b[3]}]
+set_property PACKAGE_PIN M30 [get_ports {fmc1_la_n_b[4]}]
+set_property PACKAGE_PIN M27 [get_ports {fmc1_la_n_b[5]}]
+set_property PACKAGE_PIN N30 [get_ports {fmc1_la_n_b[6]}]
+set_property PACKAGE_PIN N26 [get_ports {fmc1_la_n_b[7]}]
+set_property PACKAGE_PIN N20 [get_ports {fmc1_la_n_b[8]}]
+set_property PACKAGE_PIN N22 [get_ports {fmc1_la_n_b[9]}]
+set_property PACKAGE_PIN N24 [get_ports {fmc1_la_n_b[10]}]
+set_property PACKAGE_PIN P22 [get_ports {fmc1_la_n_b[11]}]
+set_property PACKAGE_PIN M25 [get_ports {fmc1_la_n_b[12]}]
+set_property PACKAGE_PIN M23 [get_ports {fmc1_la_n_b[13]}]
+set_property PACKAGE_PIN A23 [get_ports {fmc1_la_n_b[14]}]
+set_property PACKAGE_PIN D23 [get_ports {fmc1_la_n_b[15]}]
+set_property PACKAGE_PIN E25 [get_ports {fmc1_la_n_b[16]}]
+set_property PACKAGE_PIN D24 [get_ports {fmc1_la_n_b[17]}]
+set_property PACKAGE_PIN E26 [get_ports {fmc1_la_n_b[18]}]
+set_property PACKAGE_PIN G24 [get_ports {fmc1_la_n_b[19]}]
+set_property PACKAGE_PIN A27 [get_ports {fmc1_la_n_b[20]}]
+set_property PACKAGE_PIN B24 [get_ports {fmc1_la_n_b[21]}]
+set_property PACKAGE_PIN A28 [get_ports {fmc1_la_n_b[22]}]
+set_property PACKAGE_PIN A26 [get_ports {fmc1_la_n_b[23]}]
+set_property PACKAGE_PIN C26 [get_ports {fmc1_la_n_b[24]}]
+set_property PACKAGE_PIN B25 [get_ports {fmc1_la_n_b[25]}]
+set_property PACKAGE_PIN C27 [get_ports {fmc1_la_n_b[26]}]
+set_property PACKAGE_PIN D28 [get_ports {fmc1_la_n_b[27]}]
+set_property PACKAGE_PIN B29 [get_ports {fmc1_la_n_b[28]}]
+set_property PACKAGE_PIN C30 [get_ports {fmc1_la_n_b[29]}]
+set_property PACKAGE_PIN A30 [get_ports {fmc1_la_n_b[30]}]
+set_property PACKAGE_PIN E30 [get_ports {fmc1_la_n_b[31]}]
+set_property PACKAGE_PIN H25 [get_ports {fmc1_la_n_b[32]}]
+set_property PACKAGE_PIN F28 [get_ports {fmc1_la_n_b[33]}]
+set_property PACKAGE_PIN Y23 [get_ports {p2_p_b[0]}]
+set_property PACKAGE_PIN Y21 [get_ports {p2_p_b[1]}]
+set_property PACKAGE_PIN AB22 [get_ports {p2_p_b[2]}]
+set_property PACKAGE_PIN AA22 [get_ports {p2_p_b[3]}]
+set_property PACKAGE_PIN AC20 [get_ports {p2_p_b[4]}]
+set_property PACKAGE_PIN AA20 [get_ports {p2_p_b[5]}]
+set_property PACKAGE_PIN AB24 [get_ports {p2_p_b[6]}]
+set_property PACKAGE_PIN AC22 [get_ports {p2_p_b[7]}]
+set_property PACKAGE_PIN AC24 [get_ports {p2_p_b[8]}]
+set_property PACKAGE_PIN AD21 [get_ports {p2_p_b[9]}]
+set_property PACKAGE_PIN Y24 [get_ports {p2_n_b[0]}]
+set_property PACKAGE_PIN AA21 [get_ports {p2_n_b[1]}]
+set_property PACKAGE_PIN AB23 [get_ports {p2_n_b[2]}]
+set_property PACKAGE_PIN AA23 [get_ports {p2_n_b[3]}]
+set_property PACKAGE_PIN AC21 [get_ports {p2_n_b[4]}]
+set_property PACKAGE_PIN AB20 [get_ports {p2_n_b[5]}]
+set_property PACKAGE_PIN AC25 [get_ports {p2_n_b[6]}]
+set_property PACKAGE_PIN AD22 [get_ports {p2_n_b[7]}]
+set_property PACKAGE_PIN AD24 [get_ports {p2_n_b[8]}]
+set_property PACKAGE_PIN AE21 [get_ports {p2_n_b[9]}]
+set_property PACKAGE_PIN G27 [get_ports {p2_p_b[10]}]
+set_property PACKAGE_PIN G29 [get_ports {p2_p_b[11]}]
+set_property PACKAGE_PIN H26 [get_ports {p2_p_b[12]}]
+set_property PACKAGE_PIN H30 [get_ports {p2_p_b[13]}]
+set_property PACKAGE_PIN L16 [get_ports {p2_p_b[14]}]
+set_property PACKAGE_PIN L15 [get_ports {p2_p_b[15]}]
+set_property PACKAGE_PIN L12 [get_ports {p2_p_b[16]}]
+set_property PACKAGE_PIN K13 [get_ports {p2_p_b[17]}]
+set_property PACKAGE_PIN K14 [get_ports {p2_p_b[18]}]
+set_property PACKAGE_PIN L11 [get_ports {p2_p_b[19]}]
+set_property PACKAGE_PIN G15 [get_ports {p2_n_b[10]}]
+set_property PACKAGE_PIN J12 [get_ports {p2_n_b[11]}]
+set_property PACKAGE_PIN H16 [get_ports {p2_n_b[12]}]
+set_property PACKAGE_PIN H12 [get_ports {p2_n_b[13]}]
+set_property PACKAGE_PIN G14 [get_ports {p2_n_b[14]}]
+set_property PACKAGE_PIN F13 [get_ports {p2_n_b[15]}]
+set_property PACKAGE_PIN D13 [get_ports {p2_n_b[16]}]
+set_property PACKAGE_PIN E13 [get_ports {p2_n_b[17]}]
+set_property PACKAGE_PIN B12 [get_ports {p2_n_b[18]}]
+set_property PACKAGE_PIN E11 [get_ports {p2_n_b[19]}]
+set_property PACKAGE_PIN Y20 [get_ports {rst_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {rst_n_i}]
+set_property PACKAGE_PIN AE23 [get_ports {vme_write_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_write_n_i}]
+set_property PACKAGE_PIN AF23 [get_ports {vme_sysreset_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_sysreset_n_i}]
+set_property PACKAGE_PIN AD23 [get_ports {vme_retry_oe_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_retry_oe_o}]
+set_property PACKAGE_PIN AE24 [get_ports {vme_retry_n_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_retry_n_o}]
+set_property PACKAGE_PIN AF22 [get_ports {vme_lword_n_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_lword_n_b}]
+set_property PACKAGE_PIN AG23 [get_ports {vme_iackout_n_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_iackout_n_o}]
+set_property PACKAGE_PIN AG24 [get_ports {vme_iackin_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_iackin_n_i}]
+set_property PACKAGE_PIN AH24 [get_ports {vme_iack_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_iack_n_i}]
+set_property PACKAGE_PIN AJ24 [get_ports {vme_gap_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_gap_i}]
+set_property PACKAGE_PIN AK25 [get_ports {vme_dtack_oe_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_dtack_oe_o}]
+set_property PACKAGE_PIN AE25 [get_ports {vme_dtack_n_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_dtack_n_o}]
+set_property PACKAGE_PIN AF25 [get_ports {vme_ds_n_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ds_n_i[0]}]
+set_property PACKAGE_PIN AK23 [get_ports {vme_ds_n_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ds_n_i[1]}]
+set_property PACKAGE_PIN AK24 [get_ports {vme_data_oe_n_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_oe_n_o}]
+set_property PACKAGE_PIN AG25 [get_ports {vme_data_dir_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_dir_o}]
+set_property PACKAGE_PIN AH25 [get_ports {vme_berr_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_berr_o}]
+set_property PACKAGE_PIN AF20 [get_ports {vme_as_n_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_as_n_i}]
+set_property PACKAGE_PIN AF21 [get_ports {vme_addr_oe_n_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_oe_n_o}]
+set_property PACKAGE_PIN AG22 [get_ports {vme_addr_dir_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_dir_o}]
+set_property PACKAGE_PIN AH22 [get_ports {vme_irq_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[1]}]
+set_property PACKAGE_PIN AJ22 [get_ports {vme_irq_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[2]}]
+set_property PACKAGE_PIN AJ23 [get_ports {vme_irq_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[3]}]
+set_property PACKAGE_PIN AG20 [get_ports {vme_irq_o[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[4]}]
+set_property PACKAGE_PIN AH20 [get_ports {vme_irq_o[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[5]}]
+set_property PACKAGE_PIN AH21 [get_ports {vme_irq_o[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[6]}]
+set_property PACKAGE_PIN AJ21 [get_ports {vme_irq_o[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[7]}]
+set_property PACKAGE_PIN AK20 [get_ports {vme_ga_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {vme_ga_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[1]}]
+set_property PACKAGE_PIN AE20 [get_ports {vme_ga_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[2]}]
+set_property PACKAGE_PIN Y25 [get_ports {vme_ga_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[3]}]
+set_property PACKAGE_PIN Y26 [get_ports {vme_ga_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[4]}]
+set_property PACKAGE_PIN AA26 [get_ports {vme_data_b[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[0]}]
+set_property PACKAGE_PIN W27 [get_ports {vme_data_b[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[1]}]
+set_property PACKAGE_PIN W28 [get_ports {vme_data_b[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[2]}]
+set_property PACKAGE_PIN Y28 [get_ports {vme_data_b[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[3]}]
+set_property PACKAGE_PIN AA28 [get_ports {vme_data_b[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[4]}]
+set_property PACKAGE_PIN W29 [get_ports {vme_data_b[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[5]}]
+set_property PACKAGE_PIN Y29 [get_ports {vme_data_b[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[6]}]
+set_property PACKAGE_PIN AA27 [get_ports {vme_data_b[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[7]}]
+set_property PACKAGE_PIN AB28 [get_ports {vme_data_b[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[8]}]
+set_property PACKAGE_PIN AA25 [get_ports {vme_data_b[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[9]}]
+set_property PACKAGE_PIN AB25 [get_ports {vme_data_b[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[10]}]
+set_property PACKAGE_PIN AC29 [get_ports {vme_data_b[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[11]}]
+set_property PACKAGE_PIN AC30 [get_ports {vme_data_b[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[12]}]
+set_property PACKAGE_PIN Y30 [get_ports {vme_data_b[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[13]}]
+set_property PACKAGE_PIN AA30 [get_ports {vme_data_b[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[14]}]
+set_property PACKAGE_PIN AD29 [get_ports {vme_data_b[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[15]}]
+set_property PACKAGE_PIN AE29 [get_ports {vme_data_b[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[16]}]
+set_property PACKAGE_PIN AB29 [get_ports {vme_data_b[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[17]}]
+set_property PACKAGE_PIN AB30 [get_ports {vme_data_b[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[18]}]
+set_property PACKAGE_PIN AD27 [get_ports {vme_data_b[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[19]}]
+set_property PACKAGE_PIN AD28 [get_ports {vme_data_b[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[20]}]
+set_property PACKAGE_PIN AB27 [get_ports {vme_data_b[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[21]}]
+set_property PACKAGE_PIN AC27 [get_ports {vme_data_b[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[22]}]
+set_property PACKAGE_PIN AG29 [get_ports {vme_data_b[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[23]}]
+set_property PACKAGE_PIN AH29 [get_ports {vme_data_b[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[24]}]
+set_property PACKAGE_PIN AE28 [get_ports {vme_data_b[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[25]}]
+set_property PACKAGE_PIN AF28 [get_ports {vme_data_b[26]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[26]}]
+set_property PACKAGE_PIN AK29 [get_ports {vme_data_b[27]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[27]}]
+set_property PACKAGE_PIN AK30 [get_ports {vme_data_b[28]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[28]}]
+set_property PACKAGE_PIN AE30 [get_ports {vme_data_b[29]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[29]}]
+set_property PACKAGE_PIN AF30 [get_ports {vme_data_b[30]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[30]}]
+set_property PACKAGE_PIN AJ28 [get_ports {vme_data_b[31]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[31]}]
+set_property PACKAGE_PIN AJ29 [get_ports {vme_am_i[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[0]}]
+set_property PACKAGE_PIN AG30 [get_ports {vme_am_i[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[1]}]
+set_property PACKAGE_PIN AH30 [get_ports {vme_am_i[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[2]}]
+set_property PACKAGE_PIN AC26 [get_ports {vme_am_i[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[3]}]
+set_property PACKAGE_PIN AD26 [get_ports {vme_am_i[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[4]}]
+set_property PACKAGE_PIN AJ27 [get_ports {vme_am_i[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[5]}]
+set_property PACKAGE_PIN AK28 [get_ports {vme_addr_b[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[1]}]
+set_property PACKAGE_PIN AG27 [get_ports {vme_addr_b[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[2]}]
+set_property PACKAGE_PIN AG28 [get_ports {vme_addr_b[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[3]}]
+set_property PACKAGE_PIN AH26 [get_ports {vme_addr_b[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[4]}]
+set_property PACKAGE_PIN AH27 [get_ports {vme_addr_b[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[5]}]
+set_property PACKAGE_PIN AF26 [get_ports {vme_addr_b[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[6]}]
+set_property PACKAGE_PIN AF27 [get_ports {vme_addr_b[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[7]}]
+set_property PACKAGE_PIN AJ26 [get_ports {vme_addr_b[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[8]}]
+set_property PACKAGE_PIN AK26 [get_ports {vme_addr_b[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[9]}]
+set_property PACKAGE_PIN AE26 [get_ports {vme_addr_b[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[10]}]
+set_property PACKAGE_PIN G19 [get_ports {vme_addr_b[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[11]}]
+set_property PACKAGE_PIN K18 [get_ports {vme_addr_b[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[12]}]
+set_property PACKAGE_PIN J18 [get_ports {vme_addr_b[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[13]}]
+set_property PACKAGE_PIN H20 [get_ports {vme_addr_b[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[14]}]
+set_property PACKAGE_PIN G20 [get_ports {vme_addr_b[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[15]}]
+set_property PACKAGE_PIN J17 [get_ports {vme_addr_b[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[16]}]
+set_property PACKAGE_PIN H17 [get_ports {vme_addr_b[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[17]}]
+set_property PACKAGE_PIN J19 [get_ports {vme_addr_b[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[18]}]
+set_property PACKAGE_PIN H19 [get_ports {vme_addr_b[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[19]}]
+set_property PACKAGE_PIN L17 [get_ports {vme_addr_b[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[20]}]
+set_property PACKAGE_PIN L18 [get_ports {vme_addr_b[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[21]}]
+set_property PACKAGE_PIN K19 [get_ports {vme_addr_b[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[22]}]
+set_property PACKAGE_PIN K20 [get_ports {vme_addr_b[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[23]}]
+set_property PACKAGE_PIN H21 [get_ports {vme_addr_b[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[24]}]
+set_property PACKAGE_PIN H22 [get_ports {vme_addr_b[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[25]}]
+set_property PACKAGE_PIN D21 [get_ports {vme_addr_b[26]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[26]}]
+set_property PACKAGE_PIN C21 [get_ports {vme_addr_b[27]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[27]}]
+set_property PACKAGE_PIN G22 [get_ports {vme_addr_b[28]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[28]}]
+set_property PACKAGE_PIN F22 [get_ports {vme_addr_b[29]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[29]}]
+set_property PACKAGE_PIN D22 [get_ports {vme_addr_b[30]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[30]}]
+set_property PACKAGE_PIN C22 [get_ports {vme_addr_b[31]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[31]}]
+set_property PACKAGE_PIN Y14 [get_ports {vme_noga_i[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {vme_noga_i[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {vme_noga_i[2]}]
+set_property PACKAGE_PIN AG15 [get_ports {vme_noga_i[3]}]
+set_property PACKAGE_PIN AH15 [get_ports {vme_noga_i[4]}]
+set_property PACKAGE_PIN AH16 [get_ports {vme_use_ga_i}]
+set_property PACKAGE_PIN R19 [get_ports {pll20dac_din_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_din_o}]
+set_property PACKAGE_PIN W19 [get_ports {pll20dac_sclk_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sclk_o}]
+set_property PACKAGE_PIN M19 [get_ports {pll20dac_sync_n_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sync_n_o}]
+set_property PACKAGE_PIN P19 [get_ports {pll25dac_din_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_din_o}]
+set_property PACKAGE_PIN F23 [get_ports {pll25dac_sclk_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sclk_o}]
+set_property PACKAGE_PIN G25 [get_ports {pll25dac_sync_n_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sync_n_o}]
+set_property PACKAGE_PIN Y2 [get_ports {sfp_txp_o}]
+set_property PACKAGE_PIN Y1 [get_ports {sfp_txn_o}]
+set_property PACKAGE_PIN AA4 [get_ports {sfp_rxp_i}]
+set_property PACKAGE_PIN AA3 [get_ports {sfp_rxn_i}]
+set_property PACKAGE_PIN AJ16 [get_ports {sfp_mod_def0_i}]
+set_property PACKAGE_PIN F21 [get_ports {sfp_mod_def1_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sfp_mod_def1_b}]
+set_property PACKAGE_PIN E21 [get_ports {sfp_mod_def2_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sfp_mod_def2_b}]
+set_property PACKAGE_PIN F20 [get_ports {sfp_rate_select_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sfp_rate_select_o}]
+set_property PACKAGE_PIN AF15 [get_ports {sfp_tx_fault_i}]
+set_property PACKAGE_PIN E20 [get_ports {sfp_tx_disable_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {sfp_tx_disable_o}]
+set_property PACKAGE_PIN AG14 [get_ports {sfp_los_i}]
+set_property PACKAGE_PIN D17 [get_ports {carrier_scl_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {carrier_scl_b}]
+set_property PACKAGE_PIN D18 [get_ports {carrier_sda_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {carrier_sda_b}]
+set_property PACKAGE_PIN AH17 [get_ports {pcbrev_i[0]}]
+set_property PACKAGE_PIN AJ17 [get_ports {pcbrev_i[1]}]
+set_property PACKAGE_PIN AE16 [get_ports {pcbrev_i[2]}]
+set_property PACKAGE_PIN AF16 [get_ports {pcbrev_i[3]}]
+set_property PACKAGE_PIN AJ19 [get_ports {pcbrev_i[4]}]
+set_property PACKAGE_PIN E19 [get_ports {onewire_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {onewire_b}]
+set_property PACKAGE_PIN D19 [get_ports {uart_rxd_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {uart_rxd_i}]
+set_property PACKAGE_PIN D16 [get_ports {uart_txd_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {uart_txd_o}]
+set_property PACKAGE_PIN C16 [get_ports {spi_ncs_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {spi_ncs_o}]
+set_property PACKAGE_PIN G18 [get_ports {spi_mosi_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {spi_mosi_o}]
+set_property PACKAGE_PIN F18 [get_ports {spi_miso_i}]
+set_property IOSTANDARD LVCMOS33 [get_ports {spi_miso_i}]
+set_property PACKAGE_PIN C17 [get_ports {fp_led_line_oen_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_oen_o[0]}]
+set_property PACKAGE_PIN B17 [get_ports {fp_led_line_oen_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_oen_o[1]}]
+set_property PACKAGE_PIN G17 [get_ports {fp_led_line_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_o[0]}]
+set_property PACKAGE_PIN F17 [get_ports {fp_led_line_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_o[1]}]
+set_property PACKAGE_PIN C20 [get_ports {fp_led_column_o[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[0]}]
+set_property PACKAGE_PIN B20 [get_ports {fp_led_column_o[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[1]}]
+set_property PACKAGE_PIN A16 [get_ports {fp_led_column_o[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[2]}]
+set_property PACKAGE_PIN A17 [get_ports {fp_led_column_o[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[3]}]
+set_property PACKAGE_PIN A20 [get_ports {fp_gpio1_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio1_b}]
+set_property PACKAGE_PIN A21 [get_ports {fp_gpio2_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio2_b}]
+set_property PACKAGE_PIN B18 [get_ports {fp_gpio3_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio3_b}]
+set_property PACKAGE_PIN A18 [get_ports {fp_gpio4_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio4_b}]
+set_property PACKAGE_PIN AK19 [get_ports {fp_term_en_o[1]}]
+set_property PACKAGE_PIN AG19 [get_ports {fp_term_en_o[2]}]
+set_property PACKAGE_PIN AH19 [get_ports {fp_term_en_o[3]}]
+set_property PACKAGE_PIN AJ18 [get_ports {fp_term_en_o[4]}]
+set_property PACKAGE_PIN B22 [get_ports {fp_gpio1_a2b_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio1_a2b_o}]
+set_property PACKAGE_PIN A22 [get_ports {fp_gpio2_a2b_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio2_a2b_o}]
+set_property PACKAGE_PIN C19 [get_ports {fp_gpio34_a2b_o}]
+set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio34_a2b_o}]
+set_property PACKAGE_PIN AK18 [get_ports {fp_pushbutton_n_i}]
+set_property PACKAGE_PIN G12 [get_ports {fmc0_pg_i}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_pg_i}]
+set_property PACKAGE_PIN A11 [get_ports {fmc0_prsnt_m2c_n_i}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_prsnt_m2c_n_i}]
+set_property PACKAGE_PIN A12 [get_ports {fmc0_scl_b}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_scl_b}]
+set_property PACKAGE_PIN D11 [get_ports {fmc0_sda_b}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_sda_b}]
+set_property PACKAGE_PIN C11 [get_ports {fmc0_tck_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tck_o}]
+set_property PACKAGE_PIN F15 [get_ports {fmc0_tms_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tms_o}]
+set_property PACKAGE_PIN E16 [get_ports {fmc0_tdi_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdi_o}]
+set_property PACKAGE_PIN E14 [get_ports {fmc0_tdo_i}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdo_i}]
+set_property PACKAGE_PIN AD19 [get_ports {fmc1_pg_i}]
+set_property PACKAGE_PIN AE19 [get_ports {fmc1_prsnt_m2c_n_i}]
+set_property PACKAGE_PIN E15 [get_ports {fmc1_scl_b}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_scl_b}]
+set_property PACKAGE_PIN D14 [get_ports {fmc1_sda_b}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_sda_b}]
+set_property PACKAGE_PIN C14 [get_ports {fmc1_tck_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tck_o}]
+set_property PACKAGE_PIN B13 [get_ports {fmc1_tms_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tms_o}]
+set_property PACKAGE_PIN A13 [get_ports {fmc1_tdi_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdi_o}]
+set_property PACKAGE_PIN C15 [get_ports {fmc1_tdo_i}]
+set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdo_i}]
+set_property PACKAGE_PIN AF18 [get_ports {ddr_a_o[0]}]
+set_property PACKAGE_PIN AG18 [get_ports {ddr_a_o[1]}]
+set_property PACKAGE_PIN AF17 [get_ports {ddr_a_o[2]}]
+set_property PACKAGE_PIN AG17 [get_ports {ddr_a_o[3]}]
+set_property PACKAGE_PIN AD18 [get_ports {ddr_a_o[4]}]
+set_property PACKAGE_PIN AE18 [get_ports {ddr_a_o[5]}]
+set_property PACKAGE_PIN AD17 [get_ports {ddr_a_o[6]}]
+set_property PACKAGE_PIN AD16 [get_ports {ddr_a_o[7]}]
+set_property PACKAGE_PIN Y19 [get_ports {ddr_a_o[8]}]
+set_property PACKAGE_PIN Y18 [get_ports {ddr_a_o[9]}]
+set_property PACKAGE_PIN AA18 [get_ports {ddr_a_o[10]}]
+set_property PACKAGE_PIN AB18 [get_ports {ddr_a_o[11]}]
+set_property PACKAGE_PIN AB19 [get_ports {ddr_a_o[12]}]
+set_property PACKAGE_PIN AC19 [get_ports {ddr_a_o[13]}]
+set_property PACKAGE_PIN AB17 [get_ports {ddr_a_o[14]}]
+set_property PACKAGE_PIN AC17 [get_ports {ddr_ba_o[0]}]
+set_property PACKAGE_PIN AE15 [get_ports {ddr_ba_o[1]}]
+set_property PACKAGE_PIN AE14 [get_ports {ddr_ba_o[2]}]
+set_property PACKAGE_PIN AA15 [get_ports {ddr_cas_n_o}]
+set_property PACKAGE_PIN AC15 [get_ports {ddr_ck_n_o}]
+set_property PACKAGE_PIN AC16 [get_ports {ddr_ck_p_o}]
+set_property PACKAGE_PIN AB15 [get_ports {ddr_cke_o}]
+set_property PACKAGE_PIN AC14 [get_ports {ddr_dq_b[0]}]
+set_property PACKAGE_PIN AD14 [get_ports {ddr_dq_b[1]}]
+set_property PACKAGE_PIN AA17 [get_ports {ddr_dq_b[2]}]
+set_property PACKAGE_PIN AA16 [get_ports {ddr_dq_b[3]}]
+set_property PACKAGE_PIN Y16 [get_ports {ddr_dq_b[4]}]
+set_property PACKAGE_PIN Y15 [get_ports {ddr_dq_b[5]}]
+set_property PACKAGE_PIN AB14 [get_ports {ddr_dq_b[6]}]
+set_property PACKAGE_PIN Y13 [get_ports {ddr_dq_b[7]}]
+set_property PACKAGE_PIN AA12 [get_ports {ddr_dq_b[8]}]
+set_property PACKAGE_PIN AB12 [get_ports {ddr_dq_b[9]}]
+set_property PACKAGE_PIN AA8 [get_ports {ddr_dq_b[10]}]
+set_property PACKAGE_PIN AB8 [get_ports {ddr_dq_b[11]}]
+set_property PACKAGE_PIN AB9 [get_ports {ddr_dq_b[12]}]
+set_property PACKAGE_PIN AC9 [get_ports {ddr_dq_b[13]}]
+set_property PACKAGE_PIN Y11 [get_ports {ddr_dq_b[14]}]
+set_property PACKAGE_PIN Y10 [get_ports {ddr_dq_b[15]}]
+set_property PACKAGE_PIN AA11 [get_ports {ddr_dq_b[16]}]
+set_property PACKAGE_PIN AA10 [get_ports {ddr_dq_b[17]}]
+set_property PACKAGE_PIN AA13 [get_ports {ddr_dq_b[18]}]
+set_property PACKAGE_PIN AB13 [get_ports {ddr_dq_b[19]}]
+set_property PACKAGE_PIN AB10 [get_ports {ddr_dq_b[20]}]
+set_property PACKAGE_PIN AC10 [get_ports {ddr_dq_b[21]}]
+set_property PACKAGE_PIN AD8 [get_ports {ddr_dq_b[22]}]
+set_property PACKAGE_PIN AE8 [get_ports {ddr_dq_b[23]}]
+set_property PACKAGE_PIN AC12 [get_ports {ddr_dq_b[24]}]
+set_property PACKAGE_PIN AC11 [get_ports {ddr_dq_b[25]}]
+set_property PACKAGE_PIN AD9 [get_ports {ddr_dq_b[26]}]
+set_property PACKAGE_PIN AE9 [get_ports {ddr_dq_b[27]}]
+set_property PACKAGE_PIN AE11 [get_ports {ddr_dq_b[28]}]
+set_property PACKAGE_PIN AF11 [get_ports {ddr_dq_b[29]}]
+set_property PACKAGE_PIN AD12 [get_ports {ddr_dq_b[30]}]
+set_property PACKAGE_PIN AD11 [get_ports {ddr_dq_b[31]}]
+set_property PACKAGE_PIN AG10 [get_ports {ddr_dq_b[32]}]
+set_property PACKAGE_PIN AH10 [get_ports {ddr_dq_b[33]}]
+set_property PACKAGE_PIN AE10 [get_ports {ddr_dq_b[34]}]
+set_property PACKAGE_PIN AF10 [get_ports {ddr_dq_b[35]}]
+set_property PACKAGE_PIN AJ9 [get_ports {ddr_dq_b[36]}]
+set_property PACKAGE_PIN AK9 [get_ports {ddr_dq_b[37]}]
+set_property PACKAGE_PIN AG9 [get_ports {ddr_dq_b[38]}]
+set_property PACKAGE_PIN AH9 [get_ports {ddr_dq_b[39]}]
+set_property PACKAGE_PIN AK11 [get_ports {ddr_dq_b[40]}]
+set_property PACKAGE_PIN AK10 [get_ports {ddr_dq_b[41]}]
+set_property PACKAGE_PIN AH11 [get_ports {ddr_dq_b[42]}]
+set_property PACKAGE_PIN AJ11 [get_ports {ddr_dq_b[43]}]
+set_property PACKAGE_PIN AE13 [get_ports {ddr_dq_b[44]}]
+set_property PACKAGE_PIN AF13 [get_ports {ddr_dq_b[45]}]
+set_property PACKAGE_PIN AK14 [get_ports {ddr_dq_b[46]}]
+set_property PACKAGE_PIN AK13 [get_ports {ddr_dq_b[47]}]
+set_property PACKAGE_PIN AH14 [get_ports {ddr_dq_b[48]}]
+set_property PACKAGE_PIN AJ14 [get_ports {ddr_dq_b[49]}]
+set_property PACKAGE_PIN AJ13 [get_ports {ddr_dq_b[50]}]
+set_property PACKAGE_PIN AJ12 [get_ports {ddr_dq_b[51]}]
+set_property PACKAGE_PIN AF12 [get_ports {ddr_dq_b[52]}]
+set_property PACKAGE_PIN AG12 [get_ports {ddr_dq_b[53]}]
+set_property PACKAGE_PIN AG13 [get_ports {ddr_dq_b[54]}]
+set_property PACKAGE_PIN AH12 [get_ports {ddr_dq_b[55]}]
+set_property PACKAGE_PIN AD13 [get_ports {ddr_dq_b[56]}]
+set_property PACKAGE_PIN AC6 [get_ports {ddr_dq_b[57]}]
+set_property PACKAGE_PIN AD4 [get_ports {ddr_dq_b[58]}]
+set_property PACKAGE_PIN AD3 [get_ports {ddr_dq_b[59]}]
+set_property PACKAGE_PIN AC2 [get_ports {ddr_dq_b[60]}]
+set_property PACKAGE_PIN AC1 [get_ports {ddr_dq_b[61]}]
+set_property PACKAGE_PIN AD2 [get_ports {ddr_dq_b[62]}]
+set_property PACKAGE_PIN AD1 [get_ports {ddr_dq_b[63]}]
+set_property PACKAGE_PIN AC4 [get_ports {ddr_dqs_n_b[0]}]
+set_property PACKAGE_PIN AE6 [get_ports {ddr_dqs_n_b[1]}]
+set_property PACKAGE_PIN AD7 [get_ports {ddr_dqs_n_b[2]}]
+set_property PACKAGE_PIN AF2 [get_ports {ddr_dqs_n_b[3]}]
+set_property PACKAGE_PIN AF1 [get_ports {ddr_dqs_n_b[4]}]
+set_property PACKAGE_PIN AG3 [get_ports {ddr_dqs_n_b[5]}]
+set_property PACKAGE_PIN AE3 [get_ports {ddr_dqs_n_b[6]}]
+set_property PACKAGE_PIN AF5 [get_ports {ddr_dqs_n_b[7]}]
+set_property PACKAGE_PIN AC5 [get_ports {ddr_dqs_p_b[0]}]
+set_property PACKAGE_PIN AD6 [get_ports {ddr_dqs_p_b[1]}]
+set_property PACKAGE_PIN AC7 [get_ports {ddr_dqs_p_b[2]}]
+set_property PACKAGE_PIN AF3 [get_ports {ddr_dqs_p_b[3]}]
+set_property PACKAGE_PIN AE1 [get_ports {ddr_dqs_p_b[4]}]
+set_property PACKAGE_PIN AG4 [get_ports {ddr_dqs_p_b[5]}]
+set_property PACKAGE_PIN AE4 [get_ports {ddr_dqs_p_b[6]}]
+set_property PACKAGE_PIN AE5 [get_ports {ddr_dqs_p_b[7]}]
+set_property PACKAGE_PIN AF6 [get_ports {ddr_odt_o}]
+set_property PACKAGE_PIN AG5 [get_ports {ddr_ras_n_o}]
+set_property PACKAGE_PIN AH4 [get_ports {ddr_reset_n_o}]
+set_property PACKAGE_PIN AJ4 [get_ports {ddr_rzq_b}]
+set_property PACKAGE_PIN AH6 [get_ports {ddr_dm_o[0]}]
+set_property PACKAGE_PIN AH5 [get_ports {ddr_dm_o[1]}]
+set_property PACKAGE_PIN AG2 [get_ports {ddr_dm_o[2]}]
+set_property PACKAGE_PIN AH1 [get_ports {ddr_dm_o[3]}]
+set_property PACKAGE_PIN AH2 [get_ports {ddr_dm_o[4]}]
+set_property PACKAGE_PIN AJ2 [get_ports {ddr_dm_o[5]}]
+set_property PACKAGE_PIN AJ1 [get_ports {ddr_dm_o[6]}]
+set_property PACKAGE_PIN AK1 [get_ports {ddr_dm_o[7]}]
+set_property PACKAGE_PIN AJ3 [get_ports {ddr_we_n_o}]
+set_property PACKAGE_PIN AK3 [get_ports {ddr_cs_n_o}]
+set_property PACKAGE_PIN B19 [get_ports {si57x_scl_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {si57x_scl_b}]
+set_property PACKAGE_PIN E18 [get_ports {si57x_sda_b}]
+set_property IOSTANDARD LVCMOS33 [get_ports {si57x_sda_b}]
+set_property PACKAGE_PIN B15 [get_ports {si57x_oe_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {si57x_oe_o}]
+set_property PACKAGE_PIN B14 [get_ports {si57x_tune_o}]
+set_property IOSTANDARD LVCMOS25 [get_ports {si57x_tune_o}]
--- a/hdl/syn/svec7_test/svec7_pins.py
+++ b/hdl/syn/svec7_test/svec7_pins.py
+#!/usr/bin/python
+
+import sys
+import re
+import csv
+
+class FPGAPin:
+    def __init__(self, name, bank, pad):
+        self.name = name
+        self.bank = int(bank)
+        self.pad = pad
+        self.in_use = False
+
+def differ_by_single_letter(s1, s2):
+    if len(s1) != len(s2):
+        return False;
+
+    ch = 0
+    last = None
+    for i in range(0, len(s1)):
+        if s1[i] != s2[i]:
+            ch += 1
+            last = i
+    if ch == 1:
+        return ( s1[last], s2[last] )
+    else:
+        return False
+
+class FPGAPinFile:
+    def __init__(self, filename):
+        self.pins = []
+        for l in open(filename).readlines():
+            tok = l.split()
+            if len(tok) < 8:
+                continue
+
+            if tok[6] == "HR" or tok[6] == "HP" or tok[6] == "GTX":
+                self.pins += [ FPGAPin(tok[1], tok[3], tok[0])]
+
+    def find_pin(self, name, banks=None):
+        rv = None
+        for p in self.pins:
+            if banks and not p.bank in banks:
+                continue
+            if p.name == name:
+                return p
+        return None
+
+    def first_free_pin(self, banks=None):
+        rv = None
+        for p in self.pins:
+            if p.in_use:
+                continue
+            if banks and not p.bank in banks:
+                continue
+            return p
+
+    def first_free_diff_pair(self, banks=None):
+        rv = None
+        
+        for p_ref in self.pins:
+            if p_ref.in_use:
+                continue
+            id1 = re.match("IO_L(\d+)([PN]).+", p_ref.name)
+            if id1 == None:
+                continue
+            
+            p_ref_n = id1.group(1)
+            p_ref_pol = id1.group(2)
+            
+            for p in self.pins:
+                if p.in_use:
+                    continue
+                if banks and not p.bank in banks:
+                    continue
+                if p.bank != p_ref.bank:
+                    continue
+                id2 = re.match("IO_L(\d+)([PN]).+", p.name)
+                if id2 == None:
+                    continue
+
+
+                p_n = id2.group(1)
+                p_pol = id2.group(2)
+                
+                if p_ref_n == p_n and p_ref_pol != p_pol:
+                #    print("MAtch!")
+                    if p_ref_pol.lower() == 'p':
+                        return ( p_ref, p )
+                    else:
+                        return ( p, p_ref )
+
+        return rv
+
+    def free_pins_in_banks(self, banks):
+        for b in banks:
+            cnt_free = 0
+            cnt_total = 0
+            for p in self.pins:
+                if p.bank == b:
+                    cnt_total += 1
+                    if not p.in_use:
+                        cnt_free += 1
+            print("Bank %d: %d total, %d free pins" % (b, cnt_total, cnt_free))
+
+class Signal: 
+    def __init__(self, name, range_hi = 0, range_lo = 0, diff=False, force=None, banks=None, iostandard=None):
+        self.name = name
+        self.range_hi = range_hi
+        self.range_lo = range_lo
+        self.diff = diff
+        self.force = force
+        self.banks = banks
+        self.iostandard = iostandard
+        self.done=False
+        self.pair=None
+        self.fpga_pins={}
+        
+
+class TopLevelSignals:
+    def __init__(self):
+        self.signals=[]
+
+    def add( self, name, range_hi = 0, range_lo = 0, diff=False, force=None, banks=None, iostandard=None):
+        self.signals += [ Signal( name, range_hi, range_lo, diff, force, banks, iostandard)]
+
+    def print_stats(self):
+        total = 0
+        for s in self.signals:
+            total += (s.range_hi + 1 - s.range_lo)
+
+        print("Total signals : %d", total)
+
+    def find_diff_pair(self, p_ref):
+        rv = None
+        
+        for p in self.signals:
+            ch = 0
+            #print("%s %s", p.name, p_ref.name)
+            if len(p.name) != len(p_ref.name):
+                continue
+            for i in range(0, len(p_ref.name)):
+                #print ( p.name[i].lower() )
+                if p.name[i].lower() != p_ref.name[i].lower():
+                    ch+=1
+                if p.name[i].lower()=="p" and p_ref.name[i].lower()=="n":
+                    #print("MATCH")
+                    rv = (p, p_ref)
+                elif p.name[i].lower()=="n" and p_ref.name[i].lower()=="p":
+                    #print("MATCH2")
+                    rv = (p_ref, p)
+            if ch == 1 and rv:
+                return rv
+
+        return rv
+
+fpga_pins = FPGAPinFile( 'xc7k325tffg900pkg.txt')
+
+signals = TopLevelSignals()
+
+banks_hp = [32, 33, 34]
+banks_hr_33 = [12, 13, 17]
+banks_hr_25 = [14, 15, 16, 18]
+
+banks_hr_all = [12, 13, 14, 15, 16, 17, 18]
+
+signals.add("clk_20m_vcxo_i", force="IO_L13P_T2_MRCC_13")
+signals.add("clk_62m5_pllref_p_i", force="IO_L12P_T1_MRCC_12", iostandard="LVDS")
+signals.add("clk_62m5_pllref_n_i", force="IO_L12N_T1_MRCC_12", iostandard="LVDS")
+signals.add("clk_125m_gtx_n_i", force="MGTREFCLK0N_115")
+signals.add("clk_125m_gtx_p_i", force="MGTREFCLK0P_115")
+signals.add("clk_fpga2_p_i", force="IO_L13P_T2_MRCC_12", iostandard="LVDS")
+signals.add("clk_fpga2_n_i", force="IO_L13N_T2_MRCC_12", iostandard="LVDS")
+signals.add("clk_si57x_p_i", force="IO_L12P_T1_MRCC_13", iostandard="LVDS")
+signals.add("clk_si57x_n_i", force="IO_L12N_T1_MRCC_13", iostandard="LVDS")
+
+signals.add("fmc0_clk_m2c_p_i[0]", force="IO_L12P_T1_MRCC_AD5P_15", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc0_clk_m2c_n_i[0]", force="IO_L12N_T1_MRCC_AD5N_15", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc0_clk_m2c_p_i[1]", force="IO_L13P_T2_MRCC_15", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc0_clk_m2c_n_i[1]", force="IO_L13N_T2_MRCC_15", banks=banks_hr_25, iostandard="LVDS_25")
+
+signals.add("fmc1_clk_m2c_p_i[0]", force="IO_L12P_T1_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc1_clk_m2c_n_i[0]", force="IO_L12N_T1_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc1_clk_m2c_p_i[1]", force="IO_L13P_T2_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
+signals.add("fmc1_clk_m2c_n_i[1]", force="IO_L13P_T2_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
+
+signals.add("fmc0_la_p_b", 33, 0, diff=True, banks=banks_hr_25)
+signals.add("fmc0_la_n_b", 33, 0, diff=True, banks=banks_hr_25)
+signals.add("fmc1_la_p_b", 33, 0, diff=True, banks=banks_hr_25)
+signals.add("fmc1_la_n_b", 33, 0, diff=True, banks=banks_hr_25)
+
+signals.add("p2_p_b", 9, 0, diff=True, banks=banks_hr_33)
+signals.add("p2_n_b", 9, 0, diff=True, banks=banks_hr_33)
+
+signals.add("p2_p_b", 19, 10, diff=True, banks=banks_hr_25)
+signals.add("p2_n_b", 19, 10, diff=True, banks=banks_hr_25)
+
+
+signals.add("rst_n_i", banks = banks_hr_33)
+signals.add("vme_write_n_i", banks = banks_hr_33)
+signals.add("vme_sysreset_n_i", banks = banks_hr_33)
+signals.add("vme_retry_oe_o", banks = banks_hr_33)
+signals.add("vme_retry_n_o", banks = banks_hr_33)
+signals.add("vme_lword_n_b", banks = banks_hr_33)
+signals.add("vme_iackout_n_o", banks = banks_hr_33)
+signals.add("vme_iackin_n_i", banks = banks_hr_33)
+signals.add("vme_iack_n_i", banks = banks_hr_33)
+signals.add("vme_gap_i", banks = banks_hr_33)
+signals.add("vme_dtack_oe_o", banks = banks_hr_33)
+signals.add("vme_dtack_n_o", banks = banks_hr_33)
+signals.add("vme_ds_n_i", 1, 0, banks = banks_hr_33)
+signals.add("vme_data_oe_n_o", banks = banks_hr_33)
+signals.add("vme_data_dir_o", banks = banks_hr_33)
+signals.add("vme_berr_o", banks = banks_hr_33)
+signals.add("vme_as_n_i", banks = banks_hr_33)
+signals.add("vme_addr_oe_n_o", banks = banks_hr_33)
+signals.add("vme_addr_dir_o", banks = banks_hr_33)
+signals.add("vme_irq_o",        7, 1, banks = banks_hr_33)
+signals.add("vme_ga_i",         4, 0, banks = banks_hr_33)
+signals.add("vme_data_b",       31, 0, banks = banks_hr_33)
+signals.add("vme_am_i",         5, 0, banks = banks_hr_33)
+signals.add("vme_addr_b",       31, 1, banks = banks_hr_33)
+signals.add("vme_noga_i",       4, 0, banks = banks_hp)
+signals.add("vme_use_ga_i", banks = banks_hp)
+signals.add("pll20dac_din_o", banks=banks_hr_all),
+signals.add("pll20dac_sclk_o", banks=banks_hr_all),
+signals.add("pll20dac_sync_n_o", banks=banks_hr_all),
+signals.add("pll25dac_din_o", banks=banks_hr_all),
+signals.add("pll25dac_sclk_o", banks=banks_hr_all),
+signals.add("pll25dac_sync_n_o", banks=banks_hr_all),
+signals.add("sfp_txp_o", force="MGTXTXP0_115")
+signals.add("sfp_txn_o", force="MGTXTXN0_115")
+signals.add("sfp_rxp_i", force="MGTXRXP0_115")
+signals.add("sfp_rxn_i", force="MGTXRXN0_115")
+signals.add("sfp_mod_def0_i", banks=banks_hp),
+signals.add("sfp_mod_def1_b", banks=banks_hr_all),
+signals.add("sfp_mod_def2_b", banks=banks_hr_all),
+signals.add("sfp_rate_select_o", banks=banks_hr_all),
+signals.add("sfp_tx_fault_i", banks=banks_hp),
+signals.add("sfp_tx_disable_o", banks=banks_hr_all),
+signals.add("sfp_los_i", banks=banks_hp),
+signals.add("carrier_scl_b", banks=banks_hr_all),
+signals.add("carrier_sda_b", banks=banks_hr_all),
+signals.add("pcbrev_i", 4, 0, banks=banks_hp),
+signals.add("onewire_b", banks=banks_hr_all),
+signals.add("uart_rxd_i", banks=banks_hr_all),
+signals.add("uart_txd_o", banks=banks_hr_all),
+signals.add("spi_ncs_o", banks=banks_hr_all),
+signals.add("spi_mosi_o", banks=banks_hr_all),
+signals.add("spi_miso_i", banks=banks_hr_all),
+
+signals.add("fp_led_line_oen_o", 1,0, banks=banks_hr_all)
+signals.add("fp_led_line_o", 1,0, banks=banks_hr_all)
+signals.add("fp_led_column_o",   3,0, banks=banks_hr_all)
+
+signals.add("fp_gpio1_b", banks=banks_hr_all),
+signals.add("fp_gpio2_b", banks=banks_hr_all),
+signals.add("fp_gpio3_b", banks=banks_hr_all),
+signals.add("fp_gpio4_b", banks=banks_hr_all),
+signals.add("fp_term_en_o",4, 1, banks=banks_hp)
+signals.add("fp_gpio1_a2b_o", banks=banks_hr_all)
+signals.add("fp_gpio2_a2b_o", banks=banks_hr_all)
+signals.add("fp_gpio34_a2b_o", banks=banks_hr_all)
+
+signals.add("fp_pushbutton_n_i", banks=banks_hp),
+
+signals.add("fmc0_pg_i", banks=banks_hr_25)
+signals.add("fmc0_prsnt_m2c_n_i", banks=banks_hr_25)
+
+signals.add("fmc0_scl_b", banks=banks_hr_25)
+signals.add("fmc0_sda_b", banks=banks_hr_25)
+signals.add("fmc0_tck_o", banks=banks_hr_25)
+signals.add("fmc0_tms_o", banks=banks_hr_25)
+signals.add("fmc0_tdi_o", banks=banks_hr_25)
+signals.add("fmc0_tdo_i", banks=banks_hr_25)
+
+
+signals.add("fmc1_pg_i", banks=banks_hp)
+signals.add("fmc1_prsnt_m2c_n_i", banks=banks_hp)
+
+signals.add("fmc1_scl_b", banks=banks_hr_25)
+signals.add("fmc1_sda_b", banks=banks_hr_25)
+signals.add("fmc1_tck_o", banks=banks_hr_25)
+signals.add("fmc1_tms_o", banks=banks_hr_25)
+signals.add("fmc1_tdi_o", banks=banks_hr_25)
+signals.add("fmc1_tdo_i", banks=banks_hr_25)
+
+signals.add("ddr_a_o",   14, 0, banks=banks_hp)
+signals.add("ddr_ba_o",  2, 0, banks=banks_hp)
+signals.add("ddr_cas_n_o", banks=banks_hp)
+signals.add("ddr_ck_n_o",diff=True, banks=banks_hp)
+signals.add("ddr_ck_p_o",diff=True, banks=banks_hp)
+signals.add("ddr_cke_o", banks=banks_hp)
+signals.add("ddr_dq_b",  63, 0, banks=banks_hp)
+signals.add("ddr_dqs_n_b",   7, 0, diff=True, banks=banks_hp)
+signals.add("ddr_dqs_p_b",   7, 0, diff=True, banks=banks_hp)
+signals.add("ddr_odt_o", banks=banks_hp)
+signals.add("ddr_ras_n_o", banks=banks_hp)
+signals.add("ddr_reset_n_o", banks=banks_hp)
+signals.add("ddr_rzq_b", banks=banks_hp)
+signals.add("ddr_dm_o",  7, 0, banks=banks_hp)
+signals.add("ddr_we_n_o", banks=banks_hp)
+signals.add("ddr_cs_n_o", banks=banks_hp)
+signals.add("si57x_scl_b", banks=banks_hr_all)
+signals.add("si57x_sda_b", banks=banks_hr_all)
+signals.add("si57x_oe_o", banks=banks_hr_all)
+signals.add("si57x_tune_o", banks=banks_hr_all)
+
+for s in signals.signals:
+    if s.done:
+        continue
+    if s.force:
+        p = fpga_pins.find_pin(s.force)
+        if p == None:
+            print("!!!! unknown forced pin")
+        print("Force: %-30s -> %-20s" % (s.name, s.force))
+        s.done = True
+        s.fpga_pins[0] = p
+
+
+
+for s in signals.signals:
+    if s.done:
+        continue
+    if s.diff:
+        for idx in range( s.range_lo, s.range_hi + 1 ):
+            #print("Do Signal %s[%d]" % (s.name, idx))
+            pair = signals.find_diff_pair( s )
+            f_pair = fpga_pins.first_free_diff_pair( banks = s.banks )
+            if f_pair == None:
+                print("!!!! Unable to fit diff pair: %s" % s.name)
+                break
+            pair[0].done = True
+            pair[1].done = True
+            f_pair[0].in_use = True
+            f_pair[1].in_use = True
+
+    
+            pair[0].fpga_pins[idx] = f_pair[0]
+            pair[1].fpga_pins[idx] = f_pair[1]
+
+            #print("DP %s[%d] %s %s %d" %( pair[0].name, idx, f_pair[0].name, f_pair[0].pad, f_pair[0].bank ) )
+            #print("DN %s[%d] %s %s %d" %( pair[1].name, idx, f_pair[1].name, f_pair[1].pad, f_pair[1].bank ) )
+    else:
+        for idx in range( s.range_lo, s.range_hi + 1 ):
+            f_pin = fpga_pins.first_free_pin( banks = s.banks )
+            if f_pin == None:
+                print("!!!! Unable to fit pin: %s" % s.name)
+                break
+            s.done = True
+            f_pin.in_use = True
+            s.fpga_pins[idx] = f_pin
+
+            #print("D %s[%d] %s %s %d" %( s.name, idx, f_pin.name, f_pin.pad, f_pin.bank ) )
+
+f_xdc = open("out.xdc","wb")
+
+for s in signals.signals:
+    for idx in range( s.range_lo, s.range_hi + 1 ):
+        if s.range_lo == 0 and s.range_hi == 0:
+            rstring = ""
+        else:
+            rstring = "[%d]" % idx
+        f_xdc.write("set_property PACKAGE_PIN %s [get_ports {%s%s}]\n" % (s.fpga_pins[idx].pad, s.name, rstring))
+        if not s.diff:
+            iostd = None
+            if s.iostandard != None:
+                iostd = s.iostandard
+            elif s.fpga_pins[idx].bank in banks_hr_33:
+                iostd = "LVCMOS33"
+            elif s.fpga_pins[idx].bank in banks_hr_25:
+                iostd = "LVCMOS25"
+            if iostd:
+                f_xdc.write("set_property IOSTANDARD %s [get_ports {%s%s}]\n"% (iostd, s.name, rstring))
+
+fpga_pins.free_pins_in_banks([12,13,14,15,16,17,18,32,33,34])
+signals.print_stats()
+
+f_xdc.close()
\ No newline at end of file
--- a/hdl/syn/svec7_test/xc7k160tfbg676pkg.txt
+++ b/hdl/syn/svec7_test/xc7k160tfbg676pkg.txt
+Device/Package xc7k160tfbg676 8/10/2011 13:58:27                                                                                                   
+                                                                                                         
+Pin   Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
+R11   DXN_0                         NA                 0     NA            NA                  CONFIG    NA
+M12   VCCADC_0                      NA                 0     NA            NA                  CONFIG    NA
+M11   GNDADC_0                      NA                 0     NA            NA                  CONFIG    NA
+R12   DXP_0                         NA                 0     NA            NA                  CONFIG    NA
+N11   VREFN_0                       NA                 0     NA            NA                  CONFIG    NA
+P12   VREFP_0                       NA                 0     NA            NA                  CONFIG    NA
+N12   VP_0                          NA                 0     NA            NA                  CONFIG    NA
+P11   VN_0                          NA                 0     NA            NA                  CONFIG    NA
+E8    VCCBATT_0                     NA                 0     NA            NA                  CONFIG    NA
+C8    CCLK_0                        NA                 0     NA            NA                  CONFIG    NA
+L8    TCK_0                         NA                 0     NA            NA                  CONFIG    NA
+N8    TMS_0                         NA                 0     NA            NA                  CONFIG    NA
+R7    TDO_0                         NA                 0     NA            NA                  CONFIG    NA
+R6    TDI_0                         NA                 0     NA            NA                  CONFIG    NA
+G7    INIT_B_0                      NA                 0     NA            NA                  CONFIG    NA
+P6    PROGRAM_B_0                   NA                 0     NA            NA                  CONFIG    NA
+P7    CFGBVS_0                      NA                 0     NA            NA                  CONFIG    NA
+J7    DONE_0                        NA                 0     NA            NA                  CONFIG    NA
+P5    M2_0                          NA                 0     NA            NA                  CONFIG    NA
+T5    M0_0                          NA                 0     NA            NA                  CONFIG    NA
+T2    M1_0                          NA                 0     NA            NA                  CONFIG    NA
+U21   IO_0_12                       NA                 12    NA            NA                  HR        7K70T
+U22   IO_L1P_T0_12                  0                  12    NA            NA                  HR        7K70T
+V22   IO_L1N_T0_12                  0                  12    NA            NA                  HR        7K70T
+U24   IO_L2P_T0_12                  0                  12    NA            NA                  HR        7K70T
+U25   IO_L2N_T0_12                  0                  12    NA            NA                  HR        7K70T
+V23   IO_L3P_T0_DQS_12              0                  12    NA            NA                  HR        7K70T
+V24   IO_L3N_T0_DQS_12              0                  12    NA            NA                  HR        7K70T
+U26   IO_L4P_T0_12                  0                  12    NA            NA                  HR        7K70T
+V26   IO_L4N_T0_12                  0                  12    NA            NA                  HR        7K70T
+W25   IO_L5P_T0_12                  0                  12    NA            NA                  HR        7K70T
+W26   IO_L5N_T0_12                  0                  12    NA            NA                  HR        7K70T
+V21   IO_L6P_T0_12                  0                  12    NA            NA                  HR        7K70T
+W21   IO_L6N_T0_VREF_12             0                  12    NA            NA                  HR        7K70T
+AA25  IO_L7P_T1_12                  1                  12    NA            NA                  HR        7K70T
+AB25  IO_L7N_T1_12                  1                  12    NA            NA                  HR        7K70T
+W23   IO_L8P_T1_12                  1                  12    NA            NA                  HR        7K70T
+W24   IO_L8N_T1_12                  1                  12    NA            NA                  HR        7K70T
+AB26  IO_L9P_T1_DQS_12              1                  12    NA            NA                  HR        7K70T
+AC26  IO_L9N_T1_DQS_12              1                  12    NA            NA                  HR        7K70T
+Y25   IO_L10P_T1_12                 1                  12    NA            NA                  HR        7K70T
+Y26   IO_L10N_T1_12                 1                  12    NA            NA                  HR        7K70T
+AA23  IO_L11P_T1_SRCC_12            1                  12    NA            NA                  HR        7K70T
+AB24  IO_L11N_T1_SRCC_12            1                  12    NA            NA                  HR        7K70T
+Y23   IO_L12P_T1_MRCC_12            1                  12    NA            NA                  HR        7K70T
+AA24  IO_L12N_T1_MRCC_12            1                  12    NA            NA                  HR        7K70T
+Y22   IO_L13P_T2_MRCC_12            2                  12    NA            NA                  HR        7K70T
+AA22  IO_L13N_T2_MRCC_12            2                  12    NA            NA                  HR        7K70T
+AC23  IO_L14P_T2_SRCC_12            2                  12    NA            NA                  HR        7K70T
+AC24  IO_L14N_T2_SRCC_12            2                  12    NA            NA                  HR        7K70T
+W20   IO_L15P_T2_DQS_12             2                  12    NA            NA                  HR        7K70T
+Y21   IO_L15N_T2_DQS_12             2                  12    NA            NA                  HR        7K70T
+AD23  IO_L16P_T2_12                 2                  12    NA            NA                  HR        7K70T
+AD24  IO_L16N_T2_12                 2                  12    NA            NA                  HR        7K70T
+AB22  IO_L17P_T2_12                 2                  12    NA            NA                  HR        7K70T
+AC22  IO_L17N_T2_12                 2                  12    NA            NA                  HR        7K70T
+AB21  IO_L18P_T2_12                 2                  12    NA            NA                  HR        7K70T
+AC21  IO_L18N_T2_12                 2                  12    NA            NA                  HR        7K70T
+AD21  IO_L19P_T3_12                 3                  12    NA            NA                  HR        7K70T
+AE21  IO_L19N_T3_VREF_12            3                  12    NA            NA                  HR        7K70T
+AF24  IO_L20P_T3_12                 3                  12    NA            NA                  HR        7K70T
+AF25  IO_L20N_T3_12                 3                  12    NA            NA                  HR        7K70T
+AD26  IO_L21P_T3_DQS_12             3                  12    NA            NA                  HR        7K70T
+AE26  IO_L21N_T3_DQS_12             3                  12    NA            NA                  HR        7K70T
+AE23  IO_L22P_T3_12                 3                  12    NA            NA                  HR        7K70T
+AF23  IO_L22N_T3_12                 3                  12    NA            NA                  HR        7K70T
+AD25  IO_L23P_T3_12                 3                  12    NA            NA                  HR        7K70T
+AE25  IO_L23N_T3_12                 3                  12    NA            NA                  HR        7K70T
+AE22  IO_L24P_T3_12                 3                  12    NA            NA                  HR        7K70T
+AF22  IO_L24N_T3_12                 3                  12    NA            NA                  HR        7K70T
+Y20   IO_25_12                      NA                 12    NA            NA                  HR        7K70T
+N16   IO_0_13                       NA                 13    NA            NA                  HR        NA
+K25   IO_L1P_T0_13                  0                  13    NA            NA                  HR        NA
+K26   IO_L1N_T0_13                  0                  13    NA            NA                  HR        NA
+R26   IO_L2P_T0_13                  0                  13    NA            NA                  HR        NA
+P26   IO_L2N_T0_13                  0                  13    NA            NA                  HR        NA
+M25   IO_L3P_T0_DQS_13              0                  13    NA            NA                  HR        NA
+L25   IO_L3N_T0_DQS_13              0                  13    NA            NA                  HR        NA
+P24   IO_L4P_T0_13                  0                  13    NA            NA                  HR        NA
+N24   IO_L4N_T0_13                  0                  13    NA            NA                  HR        NA
+N26   IO_L5P_T0_13                  0                  13    NA            NA                  HR        NA
+M26   IO_L5N_T0_13                  0                  13    NA            NA                  HR        NA
+R25   IO_L6P_T0_13                  0                  13    NA            NA                  HR        NA
+P25   IO_L6N_T0_VREF_13             0                  13    NA            NA                  HR        NA
+N19   IO_L7P_T1_13                  1                  13    NA            NA                  HR        NA
+M20   IO_L7N_T1_13                  1                  13    NA            NA                  HR        NA
+M24   IO_L8P_T1_13                  1                  13    NA            NA                  HR        NA
+L24   IO_L8N_T1_13                  1                  13    NA            NA                  HR        NA
+P19   IO_L9P_T1_DQS_13              1                  13    NA            NA                  HR        NA
+P20   IO_L9N_T1_DQS_13              1                  13    NA            NA                  HR        NA
+M21   IO_L10P_T1_13                 1                  13    NA            NA                  HR        NA
+M22   IO_L10N_T1_13                 1                  13    NA            NA                  HR        NA
+P23   IO_L11P_T1_SRCC_13            1                  13    NA            NA                  HR        NA
+N23   IO_L11N_T1_SRCC_13            1                  13    NA            NA                  HR        NA
+N21   IO_L12P_T1_MRCC_13            1                  13    NA            NA                  HR        NA
+N22   IO_L12N_T1_MRCC_13            1                  13    NA            NA                  HR        NA
+R21   IO_L13P_T2_MRCC_13            2                  13    NA            NA                  HR        NA
+P21   IO_L13N_T2_MRCC_13            2                  13    NA            NA                  HR        NA
+R22   IO_L14P_T2_SRCC_13            2                  13    NA            NA                  HR        NA
+R23   IO_L14N_T2_SRCC_13            2                  13    NA            NA                  HR        NA
+T24   IO_L15P_T2_DQS_13             2                  13    NA            NA                  HR        NA
+T25   IO_L15N_T2_DQS_13             2                  13    NA            NA                  HR        NA
+T20   IO_L16P_T2_13                 2                  13    NA            NA                  HR        NA
+R20   IO_L16N_T2_13                 2                  13    NA            NA                  HR        NA
+T22   IO_L17P_T2_13                 2                  13    NA            NA                  HR        NA
+T23   IO_L17N_T2_13                 2                  13    NA            NA                  HR        NA
+U19   IO_L18P_T2_13                 2                  13    NA            NA                  HR        NA
+U20   IO_L18N_T2_13                 2                  13    NA            NA                  HR        NA
+T18   IO_L19P_T3_13                 3                  13    NA            NA                  HR        NA
+T19   IO_L19N_T3_VREF_13            3                  13    NA            NA                  HR        NA
+P16   IO_L20P_T3_13                 3                  13    NA            NA                  HR        NA
+N17   IO_L20N_T3_13                 3                  13    NA            NA                  HR        NA
+R16   IO_L21P_T3_DQS_13             3                  13    NA            NA                  HR        NA
+R17   IO_L21N_T3_DQS_13             3                  13    NA            NA                  HR        NA
+N18   IO_L22P_T3_13                 3                  13    NA            NA                  HR        NA
+M19   IO_L22N_T3_13                 3                  13    NA            NA                  HR        NA
+U17   IO_L23P_T3_13                 3                  13    NA            NA                  HR        NA
+T17   IO_L23N_T3_13                 3                  13    NA            NA                  HR        NA
+R18   IO_L24P_T3_13                 3                  13    NA            NA                  HR        NA
+P18   IO_L24N_T3_13                 3                  13    NA            NA                  HR        NA
+U16   IO_25_13                      NA                 13    NA            NA                  HR        NA
+K21   IO_0_14                       NA                 14    NA            NA                  HR        NA
+B24   IO_L1P_T0_D00_MOSI_14         0                  14    NA            NA                  HR        NA
+A25   IO_L1N_T0_D01_DIN_14          0                  14    NA            NA                  HR        NA
+B22   IO_L2P_T0_D02_14              0                  14    NA            NA                  HR        NA
+A22   IO_L2N_T0_D03_14              0                  14    NA            NA                  HR        NA
+B25   IO_L3P_T0_DQS_PUDC_B_14       0                  14    NA            NA                  HR        NA
+B26   IO_L3N_T0_DQS_EMCCLK_14       0                  14    NA            NA                  HR        NA
+A23   IO_L4P_T0_D04_14              0                  14    NA            NA                  HR        NA
+A24   IO_L4N_T0_D05_14              0                  14    NA            NA                  HR        NA
+D26   IO_L5P_T0_D06_14              0                  14    NA            NA                  HR        NA
+C26   IO_L5N_T0_D07_14              0                  14    NA            NA                  HR        NA
+C23   IO_L6P_T0_FCS_B_14            0                  14    NA            NA                  HR        NA
+C24   IO_L6N_T0_D08_VREF_14         0                  14    NA            NA                  HR        NA
+D21   IO_L7P_T1_D09_14              1                  14    NA            NA                  HR        NA
+C22   IO_L7N_T1_D10_14              1                  14    NA            NA                  HR        NA
+B20   IO_L8P_T1_D11_14              1                  14    NA            NA                  HR        NA
+A20   IO_L8N_T1_D12_14              1                  14    NA            NA                  HR        NA
+E21   IO_L9P_T1_DQS_14              1                  14    NA            NA                  HR        NA
+E22   IO_L9N_T1_DQS_D13_14          1                  14    NA            NA                  HR        NA
+C21   IO_L10P_T1_D14_14             1                  14    NA            NA                  HR        NA
+B21   IO_L10N_T1_D15_14             1                  14    NA            NA                  HR        NA
+D23   IO_L11P_T1_SRCC_14            1                  14    NA            NA                  HR        NA
+D24   IO_L11N_T1_SRCC_14            1                  14    NA            NA                  HR        NA
+F22   IO_L12P_T1_MRCC_14            1                  14    NA            NA                  HR        NA
+E23   IO_L12N_T1_MRCC_14            1                  14    NA            NA                  HR        NA
+G22   IO_L13P_T2_MRCC_14            2                  14    NA            NA                  HR        NA
+F23   IO_L13N_T2_MRCC_14            2                  14    NA            NA                  HR        NA
+G24   IO_L14P_T2_SRCC_14            2                  14    NA            NA                  HR        NA
+F24   IO_L14N_T2_SRCC_14            2                  14    NA            NA                  HR        NA
+E25   IO_L15P_T2_DQS_RDWR_B_14      2                  14    NA            NA                  HR        NA
+D25   IO_L15N_T2_DQS_DOUT_CSO_B_14  2                  14    NA            NA                  HR        NA
+G25   IO_L16P_T2_CSI_B_14           2                  14    NA            NA                  HR        NA
+G26   IO_L16N_T2_A15_D31_14         2                  14    NA            NA                  HR        NA
+F25   IO_L17P_T2_A14_D30_14         2                  14    NA            NA                  HR        NA
+E26   IO_L17N_T2_A13_D29_14         2                  14    NA            NA                  HR        NA
+J26   IO_L18P_T2_A12_D28_14         2                  14    NA            NA                  HR        NA
+H26   IO_L18N_T2_A11_D27_14         2                  14    NA            NA                  HR        NA
+H21   IO_L19P_T3_A10_D26_14         3                  14    NA            NA                  HR        NA
+G21   IO_L19N_T3_A09_D25_VREF_14    3                  14    NA            NA                  HR        NA
+H23   IO_L20P_T3_A08_D24_14         3                  14    NA            NA                  HR        NA
+H24   IO_L20N_T3_A07_D23_14         3                  14    NA            NA                  HR        NA
+J21   IO_L21P_T3_DQS_14             3                  14    NA            NA                  HR        NA
+H22   IO_L21N_T3_DQS_A06_D22_14     3                  14    NA            NA                  HR        NA
+J24   IO_L22P_T3_A05_D21_14         3                  14    NA            NA                  HR        NA
+J25   IO_L22N_T3_A04_D20_14         3                  14    NA            NA                  HR        NA
+L22   IO_L23P_T3_A03_D19_14         3                  14    NA            NA                  HR        NA
+K22   IO_L23N_T3_A02_D18_14         3                  14    NA            NA                  HR        NA
+K23   IO_L24P_T3_A01_D17_14         3                  14    NA            NA                  HR        NA
+J23   IO_L24N_T3_A00_D16_14         3                  14    NA            NA                  HR        NA
+L23   IO_25_14                      NA                 14    NA            NA                  HR        NA
+K15   IO_0_15                       NA                 15    NA            NA                  HR        NA
+C16   IO_L1P_T0_AD0P_15             0                  15    NA            NA                  HR        NA
+B16   IO_L1N_T0_AD0N_15             0                  15    NA            NA                  HR        NA
+A18   IO_L2P_T0_AD8P_15             0                  15    NA            NA                  HR        NA
+A19   IO_L2N_T0_AD8N_15             0                  15    NA            NA                  HR        NA
+B17   IO_L3P_T0_DQS_AD1P_15         0                  15    NA            NA                  HR        NA
+A17   IO_L3N_T0_DQS_AD1N_15         0                  15    NA            NA                  HR        NA
+C19   IO_L4P_T0_AD9P_15             0                  15    NA            NA                  HR        NA
+B19   IO_L4N_T0_AD9N_15             0                  15    NA            NA                  HR        NA
+C17   IO_L5P_T0_AD2P_15             0                  15    NA            NA                  HR        NA
+C18   IO_L5N_T0_AD2N_15             0                  15    NA            NA                  HR        NA
+D15   IO_L6P_T0_15                  0                  15    NA            NA                  HR        NA
+D16   IO_L6N_T0_VREF_15             0                  15    NA            NA                  HR        NA
+H16   IO_L7P_T1_AD10P_15            1                  15    NA            NA                  HR        NA
+G16   IO_L7N_T1_AD10N_15            1                  15    NA            NA                  HR        NA
+G15   IO_L8P_T1_AD3P_15             1                  15    NA            NA                  HR        NA
+F15   IO_L8N_T1_AD3N_15             1                  15    NA            NA                  HR        NA
+J15   IO_L9P_T1_DQS_AD11P_15        1                  15    NA            NA                  HR        NA
+J16   IO_L9N_T1_DQS_AD11N_15        1                  15    NA            NA                  HR        NA
+E15   IO_L10P_T1_AD4P_15            1                  15    NA            NA                  HR        NA
+E16   IO_L10N_T1_AD4N_15            1                  15    NA            NA                  HR        NA
+G17   IO_L11P_T1_SRCC_AD12P_15      1                  15    NA            NA                  HR        NA
+F18   IO_L11N_T1_SRCC_AD12N_15      1                  15    NA            NA                  HR        NA
+F17   IO_L12P_T1_MRCC_AD5P_15       1                  15    NA            NA                  HR        NA
+E17   IO_L12N_T1_MRCC_AD5N_15       1                  15    NA            NA                  HR        NA
+E18   IO_L13P_T2_MRCC_15            2                  15    NA            NA                  HR        NA
+D18   IO_L13N_T2_MRCC_15            2                  15    NA            NA                  HR        NA
+H17   IO_L14P_T2_SRCC_15            2                  15    NA            NA                  HR        NA
+H18   IO_L14N_T2_SRCC_15            2                  15    NA            NA                  HR        NA
+D19   IO_L15P_T2_DQS_15             2                  15    NA            NA                  HR        NA
+D20   IO_L15N_T2_DQS_ADV_B_15       2                  15    NA            NA                  HR        NA
+G19   IO_L16P_T2_A28_15             2                  15    NA            NA                  HR        NA
+F20   IO_L16N_T2_A27_15             2                  15    NA            NA                  HR        NA
+F19   IO_L17P_T2_A26_15             2                  15    NA            NA                  HR        NA
+E20   IO_L17N_T2_A25_15             2                  15    NA            NA                  HR        NA
+H19   IO_L18P_T2_A24_15             2                  15    NA            NA                  HR        NA
+G20   IO_L18N_T2_A23_15             2                  15    NA            NA                  HR        NA
+K20   IO_L19P_T3_A22_15             3                  15    NA            NA                  HR        NA
+J20   IO_L19N_T3_A21_VREF_15        3                  15    NA            NA                  HR        NA
+J18   IO_L20P_T3_A20_15             3                  15    NA            NA                  HR        NA
+J19   IO_L20N_T3_A19_15             3                  15    NA            NA                  HR        NA
+L19   IO_L21P_T3_DQS_15             3                  15    NA            NA                  HR        NA
+L20   IO_L21N_T3_DQS_A18_15         3                  15    NA            NA                  HR        NA
+K16   IO_L22P_T3_A17_15             3                  15    NA            NA                  HR        NA
+K17   IO_L22N_T3_A16_15             3                  15    NA            NA                  HR        NA
+M17   IO_L23P_T3_FOE_B_15           3                  15    NA            NA                  HR        NA
+L18   IO_L23N_T3_FWE_B_15           3                  15    NA            NA                  HR        NA
+L17   IO_L24P_T3_RS1_15             3                  15    NA            NA                  HR        NA
+K18   IO_L24N_T3_RS0_15             3                  15    NA            NA                  HR        NA
+M16   IO_25_15                      NA                 15    NA            NA                  HR        NA
+J8    IO_0_16                       NA                 16    NA            NA                  HR        NA
+H9    IO_L1P_T0_16                  0                  16    NA            NA                  HR        NA
+H8    IO_L1N_T0_16                  0                  16    NA            NA                  HR        NA
+G10   IO_L2P_T0_16                  0                  16    NA            NA                  HR        NA
+G9    IO_L2N_T0_16                  0                  16    NA            NA                  HR        NA
+J13   IO_L3P_T0_DQS_16              0                  16    NA            NA                  HR        NA
+H13   IO_L3N_T0_DQS_16              0                  16    NA            NA                  HR        NA
+J11   IO_L4P_T0_16                  0                  16    NA            NA                  HR        NA
+J10   IO_L4N_T0_16                  0                  16    NA            NA                  HR        NA
+H14   IO_L5P_T0_16                  0                  16    NA            NA                  HR        NA
+G14   IO_L5N_T0_16                  0                  16    NA            NA                  HR        NA
+H12   IO_L6P_T0_16                  0                  16    NA            NA                  HR        NA
+H11   IO_L6N_T0_VREF_16             0                  16    NA            NA                  HR        NA
+F9    IO_L7P_T1_16                  1                  16    NA            NA                  HR        NA
+F8    IO_L7N_T1_16                  1                  16    NA            NA                  HR        NA
+D9    IO_L8P_T1_16                  1                  16    NA            NA                  HR        NA
+D8    IO_L8N_T1_16                  1                  16    NA            NA                  HR        NA
+A9    IO_L9P_T1_DQS_16              1                  16    NA            NA                  HR        NA
+A8    IO_L9N_T1_DQS_16              1                  16    NA            NA                  HR        NA
+C9    IO_L10P_T1_16                 1                  16    NA            NA                  HR        NA
+B9    IO_L10N_T1_16                 1                  16    NA            NA                  HR        NA
+G11   IO_L11P_T1_SRCC_16            1                  16    NA            NA                  HR        NA
+F10   IO_L11N_T1_SRCC_16            1                  16    NA            NA                  HR        NA
+E10   IO_L12P_T1_MRCC_16            1                  16    NA            NA                  HR        NA
+D10   IO_L12N_T1_MRCC_16            1                  16    NA            NA                  HR        NA
+C12   IO_L13P_T2_MRCC_16            2                  16    NA            NA                  HR        NA
+C11   IO_L13N_T2_MRCC_16            2                  16    NA            NA                  HR        NA
+E11   IO_L14P_T2_SRCC_16            2                  16    NA            NA                  HR        NA
+D11   IO_L14N_T2_SRCC_16            2                  16    NA            NA                  HR        NA
+F14   IO_L15P_T2_DQS_16             2                  16    NA            NA                  HR        NA
+F13   IO_L15N_T2_DQS_16             2                  16    NA            NA                  HR        NA
+G12   IO_L16P_T2_16                 2                  16    NA            NA                  HR        NA
+F12   IO_L16N_T2_16                 2                  16    NA            NA                  HR        NA
+D14   IO_L17P_T2_16                 2                  16    NA            NA                  HR        NA
+D13   IO_L17N_T2_16                 2                  16    NA            NA                  HR        NA
+E13   IO_L18P_T2_16                 2                  16    NA            NA                  HR        NA
+E12   IO_L18N_T2_16                 2                  16    NA            NA                  HR        NA
+C14   IO_L19P_T3_16                 3                  16    NA            NA                  HR        NA
+C13   IO_L19N_T3_VREF_16            3                  16    NA            NA                  HR        NA
+B12   IO_L20P_T3_16                 3                  16    NA            NA                  HR        NA
+B11   IO_L20N_T3_16                 3                  16    NA            NA                  HR        NA
+B14   IO_L21P_T3_DQS_16             3                  16    NA            NA                  HR        NA
+A14   IO_L21N_T3_DQS_16             3                  16    NA            NA                  HR        NA
+B10   IO_L22P_T3_16                 3                  16    NA            NA                  HR        NA
+A10   IO_L22N_T3_16                 3                  16    NA            NA                  HR        NA
+B15   IO_L23P_T3_16                 3                  16    NA            NA                  HR        NA
+A15   IO_L23N_T3_16                 3                  16    NA            NA                  HR        NA
+A13   IO_L24P_T3_16                 3                  16    NA            NA                  HR        NA
+A12   IO_L24N_T3_16                 3                  16    NA            NA                  HR        NA
+J14   IO_25_16                      NA                 16    NA            NA                  HR        NA
+V13   IO_0_VRN_32                   NA                 32    VCCAUX        NA                  HP        7K70T
+AE17  IO_L1P_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AF17  IO_L1N_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AF14  IO_L2P_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AF15  IO_L2N_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AE18  IO_L3P_T0_DQS_32              0                  32    VCCAUX        NA                  HP        7K70T
+AF18  IO_L3N_T0_DQS_32              0                  32    VCCAUX        NA                  HP        7K70T
+AD15  IO_L4P_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AE15  IO_L4N_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AF19  IO_L5P_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AF20  IO_L5N_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AD16  IO_L6P_T0_32                  0                  32    VCCAUX        NA                  HP        7K70T
+AE16  IO_L6N_T0_VREF_32             0                  32    VCCAUX        NA                  HP        7K70T
+AA14  IO_L7P_T1_32                  1                  32    VCCAUX        NA                  HP        7K70T
+AA15  IO_L7N_T1_32                  1                  32    VCCAUX        NA                  HP        7K70T
+AC14  IO_L8P_T1_32                  1                  32    VCCAUX        NA                  HP        7K70T
+AD14  IO_L8N_T1_32                  1                  32    VCCAUX        NA                  HP        7K70T
+Y15   IO_L9P_T1_DQS_32              1                  32    VCCAUX        NA                  HP        7K70T
+Y16   IO_L9N_T1_DQS_32              1                  32    VCCAUX        NA                  HP        7K70T
+AB14  IO_L10P_T1_32                 1                  32    VCCAUX        NA                  HP        7K70T
+AB15  IO_L10N_T1_32                 1                  32    VCCAUX        NA                  HP        7K70T
+AA17  IO_L11P_T1_SRCC_32            1                  32    VCCAUX        NA                  HP        7K70T
+AA18  IO_L11N_T1_SRCC_32            1                  32    VCCAUX        NA                  HP        7K70T
+AB16  IO_L12P_T1_MRCC_32            1                  32    VCCAUX        NA                  HP        7K70T
+AC16  IO_L12N_T1_MRCC_32            1                  32    VCCAUX        NA                  HP        7K70T
+AC18  IO_L13P_T2_MRCC_32            2                  32    VCCAUX        NA                  HP        7K70T
+AD18  IO_L13N_T2_MRCC_32            2                  32    VCCAUX        NA                  HP        7K70T
+AB17  IO_L14P_T2_SRCC_32            2                  32    VCCAUX        NA                  HP        7K70T
+AC17  IO_L14N_T2_SRCC_32            2                  32    VCCAUX        NA                  HP        7K70T
+AD20  IO_L15P_T2_DQS_32             2                  32    VCCAUX        NA                  HP        7K70T
+AE20  IO_L15N_T2_DQS_32             2                  32    VCCAUX        NA                  HP        7K70T
+AA19  IO_L16P_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+AA20  IO_L16N_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+AC19  IO_L17P_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+AD19  IO_L17N_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+AB19  IO_L18P_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+AB20  IO_L18N_T2_32                 2                  32    VCCAUX        NA                  HP        7K70T
+Y17   IO_L19P_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+Y18   IO_L19N_T3_VREF_32            3                  32    VCCAUX        NA                  HP        7K70T
+V16   IO_L20P_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+V17   IO_L20N_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+W18   IO_L21P_T3_DQS_32             3                  32    VCCAUX        NA                  HP        7K70T
+W19   IO_L21N_T3_DQS_32             3                  32    VCCAUX        NA                  HP        7K70T
+W15   IO_L22P_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+W16   IO_L22N_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+V18   IO_L23P_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+V19   IO_L23N_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+V14   IO_L24P_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+W14   IO_L24N_T3_32                 3                  32    VCCAUX        NA                  HP        7K70T
+W13   IO_25_VRP_32                  NA                 32    VCCAUX        NA                  HP        7K70T
+U9    IO_0_VRN_33                   NA                 33    VCCAUX        NA                  HP        NA
+V11   IO_L1P_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+W11   IO_L1N_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+V8    IO_L2P_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+V7    IO_L2N_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+W10   IO_L3P_T0_DQS_33              0                  33    VCCAUX        NA                  HP        NA
+W9    IO_L3N_T0_DQS_33              0                  33    VCCAUX        NA                  HP        NA
+Y8    IO_L4P_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+Y7    IO_L4N_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+Y11   IO_L5P_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+Y10   IO_L5N_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+V9    IO_L6P_T0_33                  0                  33    VCCAUX        NA                  HP        NA
+W8    IO_L6N_T0_VREF_33             0                  33    VCCAUX        NA                  HP        NA
+AE7   IO_L7P_T1_33                  1                  33    VCCAUX        NA                  HP        NA
+AF7   IO_L7N_T1_33                  1                  33    VCCAUX        NA                  HP        NA
+AA8   IO_L8P_T1_33                  1                  33    VCCAUX        NA                  HP        NA
+AA7   IO_L8N_T1_33                  1                  33    VCCAUX        NA                  HP        NA
+AC8   IO_L9P_T1_DQS_33              1                  33    VCCAUX        NA                  HP        NA
+AD8   IO_L9N_T1_DQS_33              1                  33    VCCAUX        NA                  HP        NA
+AB7   IO_L10P_T1_33                 1                  33    VCCAUX        NA                  HP        NA
+AC7   IO_L10N_T1_33                 1                  33    VCCAUX        NA                  HP        NA
+AA9   IO_L11P_T1_SRCC_33            1                  33    VCCAUX        NA                  HP        NA
+AB9   IO_L11N_T1_SRCC_33            1                  33    VCCAUX        NA                  HP        NA
+AC9   IO_L12P_T1_MRCC_33            1                  33    VCCAUX        NA                  HP        NA
+AD9   IO_L12N_T1_MRCC_33            1                  33    VCCAUX        NA                  HP        NA
+AB11  IO_L13P_T2_MRCC_33            2                  33    VCCAUX        NA                  HP        NA
+AC11  IO_L13N_T2_MRCC_33            2                  33    VCCAUX        NA                  HP        NA
+AA10  IO_L14P_T2_SRCC_33            2                  33    VCCAUX        NA                  HP        NA
+AB10  IO_L14N_T2_SRCC_33            2                  33    VCCAUX        NA                  HP        NA
+AB12  IO_L15P_T2_DQS_33             2                  33    VCCAUX        NA                  HP        NA
+AC12  IO_L15N_T2_DQS_33             2                  33    VCCAUX        NA                  HP        NA
+AA13  IO_L16P_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+AA12  IO_L16N_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+AC13  IO_L17P_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+AD13  IO_L17N_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+Y13   IO_L18P_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+Y12   IO_L18N_T2_33                 2                  33    VCCAUX        NA                  HP        NA
+AD11  IO_L19P_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AE11  IO_L19N_T3_VREF_33            3                  33    VCCAUX        NA                  HP        NA
+AD10  IO_L20P_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AE10  IO_L20N_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AE12  IO_L21P_T3_DQS_33             3                  33    VCCAUX        NA                  HP        NA
+AF12  IO_L21N_T3_DQS_33             3                  33    VCCAUX        NA                  HP        NA
+AE8   IO_L22P_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AF8   IO_L22N_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AE13  IO_L23P_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AF13  IO_L23N_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AF10  IO_L24P_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+AF9   IO_L24N_T3_33                 3                  33    VCCAUX        NA                  HP        NA
+V12   IO_25_VRP_33                  NA                 33    VCCAUX        NA                  HP        NA
+U4    IO_0_VRN_34                   NA                 34    VCCAUX        NA                  HP        NA
+U6    IO_L1P_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+U5    IO_L1N_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+U2    IO_L2P_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+U1    IO_L2N_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+W6    IO_L3P_T0_DQS_34              0                  34    VCCAUX        NA                  HP        NA
+W5    IO_L3N_T0_DQS_34              0                  34    VCCAUX        NA                  HP        NA
+V3    IO_L4P_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+W3    IO_L4N_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+U7    IO_L5P_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+V6    IO_L5N_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+V4    IO_L6P_T0_34                  0                  34    VCCAUX        NA                  HP        NA
+W4    IO_L6N_T0_VREF_34             0                  34    VCCAUX        NA                  HP        NA
+Y3    IO_L7P_T1_34                  1                  34    VCCAUX        NA                  HP        NA
+Y2    IO_L7N_T1_34                  1                  34    VCCAUX        NA                  HP        NA
+V2    IO_L8P_T1_34                  1                  34    VCCAUX        NA                  HP        NA
+V1    IO_L8N_T1_34                  1                  34    VCCAUX        NA                  HP        NA
+AB1   IO_L9P_T1_DQS_34              1                  34    VCCAUX        NA                  HP        NA
+AC1   IO_L9N_T1_DQS_34              1                  34    VCCAUX        NA                  HP        NA
+W1    IO_L10P_T1_34                 1                  34    VCCAUX        NA                  HP        NA
+Y1    IO_L10N_T1_34                 1                  34    VCCAUX        NA                  HP        NA
+AB2   IO_L11P_T1_SRCC_34            1                  34    VCCAUX        NA                  HP        NA
+AC2   IO_L11N_T1_SRCC_34            1                  34    VCCAUX        NA                  HP        NA
+AA3   IO_L12P_T1_MRCC_34            1                  34    VCCAUX        NA                  HP        NA
+AA2   IO_L12N_T1_MRCC_34            1                  34    VCCAUX        NA                  HP        NA
+AA4   IO_L13P_T2_MRCC_34            2                  34    VCCAUX        NA                  HP        NA
+AB4   IO_L13N_T2_MRCC_34            2                  34    VCCAUX        NA                  HP        NA
+AC4   IO_L14P_T2_SRCC_34            2                  34    VCCAUX        NA                  HP        NA
+AC3   IO_L14N_T2_SRCC_34            2                  34    VCCAUX        NA                  HP        NA
+AA5   IO_L15P_T2_DQS_34             2                  34    VCCAUX        NA                  HP        NA
+AB5   IO_L15N_T2_DQS_34             2                  34    VCCAUX        NA                  HP        NA
+AB6   IO_L16P_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+AC6   IO_L16N_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+Y6    IO_L17P_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+Y5    IO_L17N_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+AD6   IO_L18P_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+AD5   IO_L18N_T2_34                 2                  34    VCCAUX        NA                  HP        NA
+AD4   IO_L19P_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AD3   IO_L19N_T3_VREF_34            3                  34    VCCAUX        NA                  HP        NA
+AD1   IO_L20P_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AE1   IO_L20N_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AF5   IO_L21P_T3_DQS_34             3                  34    VCCAUX        NA                  HP        NA
+AF4   IO_L21N_T3_DQS_34             3                  34    VCCAUX        NA                  HP        NA
+AE3   IO_L22P_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AE2   IO_L22N_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AE6   IO_L23P_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AE5   IO_L23N_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AF3   IO_L24P_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+AF2   IO_L24N_T3_34                 3                  34    VCCAUX        NA                  HP        NA
+T7    IO_25_VRP_34                  NA                 34    VCCAUX        NA                  HP        NA
+H2    MGTXTXP3_115                  NA                 115   NA            NA                  GTX       NA
+J4    MGTXRXP3_115                  NA                 115   NA            NA                  GTX       NA
+H1    MGTXTXN3_115                  NA                 115   NA            NA                  GTX       NA
+J3    MGTXRXN3_115                  NA                 115   NA            NA                  GTX       NA
+K2    MGTXTXP2_115                  NA                 115   NA            NA                  GTX       NA
+L4    MGTXRXP2_115                  NA                 115   NA            NA                  GTX       NA
+K1    MGTXTXN2_115                  NA                 115   NA            NA                  GTX       NA
+H6    MGTREFCLK0P_115               NA                 115   NA            NA                  GTX       NA
+L3    MGTXRXN2_115                  NA                 115   NA            NA                  GTX       NA
+M5    MGTAVTTRCAL_115               NA                 115   NA            NA                  GTX       NA
+H5    MGTREFCLK0N_115               NA                 115   NA            NA                  GTX       NA
+M6    MGTRREF_115                   NA                 115   NA            NA                  GTX       NA
+K5    MGTREFCLK1N_115               NA                 115   NA            NA                  GTX       NA
+K6    MGTREFCLK1P_115               NA                 115   NA            NA                  GTX       NA
+M2    MGTXTXP1_115                  NA                 115   NA            NA                  GTX       NA
+N4    MGTXRXP1_115                  NA                 115   NA            NA                  GTX       NA
+M1    MGTXTXN1_115                  NA                 115   NA            NA                  GTX       NA
+N3    MGTXRXN1_115                  NA                 115   NA            NA                  GTX       NA
+P2    MGTXTXP0_115                  NA                 115   NA            NA                  GTX       NA
+R4    MGTXRXP0_115                  NA                 115   NA            NA                  GTX       NA
+P1    MGTXTXN0_115                  NA                 115   NA            NA                  GTX       NA
+R3    MGTXRXN0_115                  NA                 115   NA            NA                  GTX       NA
+A4    MGTXTXP3_116                  NA                 116   NA            NA                  GTX       NA
+B6    MGTXRXP3_116                  NA                 116   NA            NA                  GTX       NA
+A3    MGTXTXN3_116                  NA                 116   NA            NA                  GTX       NA
+B5    MGTXRXN3_116                  NA                 116   NA            NA                  GTX       NA
+B2    MGTXTXP2_116                  NA                 116   NA            NA                  GTX       NA
+C4    MGTXRXP2_116                  NA                 116   NA            NA                  GTX       NA
+B1    MGTXTXN2_116                  NA                 116   NA            NA                  GTX       NA
+D6    MGTREFCLK0P_116               NA                 116   NA            NA                  GTX       NA
+C3    MGTXRXN2_116                  NA                 116   NA            NA                  GTX       NA
+D5    MGTREFCLK0N_116               NA                 116   NA            NA                  GTX       NA
+F5    MGTREFCLK1N_116               NA                 116   NA            NA                  GTX       NA
+F6    MGTREFCLK1P_116               NA                 116   NA            NA                  GTX       NA
+D2    MGTXTXP1_116                  NA                 116   NA            NA                  GTX       NA
+E4    MGTXRXP1_116                  NA                 116   NA            NA                  GTX       NA
+D1    MGTXTXN1_116                  NA                 116   NA            NA                  GTX       NA
+E3    MGTXRXN1_116                  NA                 116   NA            NA                  GTX       NA
+F2    MGTXTXP0_116                  NA                 116   NA            NA                  GTX       NA
+G4    MGTXRXP0_116                  NA                 116   NA            NA                  GTX       NA
+F1    MGTXTXN0_116                  NA                 116   NA            NA                  GTX       NA
+G3    MGTXRXN0_116                  NA                 116   NA            NA                  GTX       NA
+N13   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+R13   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+T12   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+U13   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+C6    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+E6    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+G6    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+J6    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+L6    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+B3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+C2    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+D3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+G2    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+H3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+L2    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+M3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+N6    MGTVCCAUX                     NA                 NA    NA            NA                  NA        NA
+A1    GND                           NA                 NA    NA            NA                  NA        NA
+A2    GND                           NA                 NA    NA            NA                  NA        NA
+A5    GND                           NA                 NA    NA            NA                  NA        NA
+A6    GND                           NA                 NA    NA            NA                  NA        NA
+A7    GND                           NA                 NA    NA            NA                  NA        NA
+A16   GND                           NA                 NA    NA            NA                  NA        NA
+A26   GND                           NA                 NA    NA            NA                  NA        NA
+AA6   GND                           NA                 NA    NA            NA                  NA        NA
+AA16  GND                           NA                 NA    NA            NA                  NA        NA
+AA26  GND                           NA                 NA    NA            NA                  NA        NA
+AB3   GND                           NA                 NA    NA            NA                  NA        NA
+AB13  GND                           NA                 NA    NA            NA                  NA        NA
+AB23  GND                           NA                 NA    NA            NA                  NA        NA
+AC10  GND                           NA                 NA    NA            NA                  NA        NA
+AC20  GND                           NA                 NA    NA            NA                  NA        NA
+AD7   GND                           NA                 NA    NA            NA                  NA        NA
+AD17  GND                           NA                 NA    NA            NA                  NA        NA
+AE4   GND                           NA                 NA    NA            NA                  NA        NA
+AE14  GND                           NA                 NA    NA            NA                  NA        NA
+AE24  GND                           NA                 NA    NA            NA                  NA        NA
+AF1   GND                           NA                 NA    NA            NA                  NA        NA
+AF11  GND                           NA                 NA    NA            NA                  NA        NA
+AF21  GND                           NA                 NA    NA            NA                  NA        NA
+B4    GND                           NA                 NA    NA            NA                  NA        NA
+B7    GND                           NA                 NA    NA            NA                  NA        NA
+B13   GND                           NA                 NA    NA            NA                  NA        NA
+B23   GND                           NA                 NA    NA            NA                  NA        NA
+C1    GND                           NA                 NA    NA            NA                  NA        NA
+C5    GND                           NA                 NA    NA            NA                  NA        NA
+C7    GND                           NA                 NA    NA            NA                  NA        NA
+C10   GND                           NA                 NA    NA            NA                  NA        NA
+C20   GND                           NA                 NA    NA            NA                  NA        NA
+D4    GND                           NA                 NA    NA            NA                  NA        NA
+D7    GND                           NA                 NA    NA            NA                  NA        NA
+D17   GND                           NA                 NA    NA            NA                  NA        NA
+E1    GND                           NA                 NA    NA            NA                  NA        NA
+E2    GND                           NA                 NA    NA            NA                  NA        NA
+E5    GND                           NA                 NA    NA            NA                  NA        NA
+E7    GND                           NA                 NA    NA            NA                  NA        NA
+E14   GND                           NA                 NA    NA            NA                  NA        NA
+E24   GND                           NA                 NA    NA            NA                  NA        NA
+F3    GND                           NA                 NA    NA            NA                  NA        NA
+F4    GND                           NA                 NA    NA            NA                  NA        NA
+F7    GND                           NA                 NA    NA            NA                  NA        NA
+F11   GND                           NA                 NA    NA            NA                  NA        NA
+F21   GND                           NA                 NA    NA            NA                  NA        NA
+G1    GND                           NA                 NA    NA            NA                  NA        NA
+G5    GND                           NA                 NA    NA            NA                  NA        NA
+G8    GND                           NA                 NA    NA            NA                  NA        NA
+G18   GND                           NA                 NA    NA            NA                  NA        NA
+H4    GND                           NA                 NA    NA            NA                  NA        NA
+H7    GND                           NA                 NA    NA            NA                  NA        NA
+H15   GND                           NA                 NA    NA            NA                  NA        NA
+H25   GND                           NA                 NA    NA            NA                  NA        NA
+J1    GND                           NA                 NA    NA            NA                  NA        NA
+J2    GND                           NA                 NA    NA            NA                  NA        NA
+J5    GND                           NA                 NA    NA            NA                  NA        NA
+J12   GND                           NA                 NA    NA            NA                  NA        NA
+J22   GND                           NA                 NA    NA            NA                  NA        NA
+K3    GND                           NA                 NA    NA            NA                  NA        NA
+K4    GND                           NA                 NA    NA            NA                  NA        NA
+K7    GND                           NA                 NA    NA            NA                  NA        NA
+K9    GND                           NA                 NA    NA            NA                  NA        NA
+K11   GND                           NA                 NA    NA            NA                  NA        NA
+K13   GND                           NA                 NA    NA            NA                  NA        NA
+K19   GND                           NA                 NA    NA            NA                  NA        NA
+L1    GND                           NA                 NA    NA            NA                  NA        NA
+L5    GND                           NA                 NA    NA            NA                  NA        NA
+L10   GND                           NA                 NA    NA            NA                  NA        NA
+L12   GND                           NA                 NA    NA            NA                  NA        NA
+L14   GND                           NA                 NA    NA            NA                  NA        NA
+L16   GND                           NA                 NA    NA            NA                  NA        NA
+L26   GND                           NA                 NA    NA            NA                  NA        NA
+M4    GND                           NA                 NA    NA            NA                  NA        NA
+M7    GND                           NA                 NA    NA            NA                  NA        NA
+M9    GND                           NA                 NA    NA            NA                  NA        NA
+M13   GND                           NA                 NA    NA            NA                  NA        NA
+M15   GND                           NA                 NA    NA            NA                  NA        NA
+M23   GND                           NA                 NA    NA            NA                  NA        NA
+N1    GND                           NA                 NA    NA            NA                  NA        NA
+N2    GND                           NA                 NA    NA            NA                  NA        NA
+N5    GND                           NA                 NA    NA            NA                  NA        NA
+N7    GND                           NA                 NA    NA            NA                  NA        NA
+N10   GND                           NA                 NA    NA            NA                  NA        NA
+N14   GND                           NA                 NA    NA            NA                  NA        NA
+N20   GND                           NA                 NA    NA            NA                  NA        NA
+P3    GND                           NA                 NA    NA            NA                  NA        NA
+P4    GND                           NA                 NA    NA            NA                  NA        NA
+P9    GND                           NA                 NA    NA            NA                  NA        NA
+P13   GND                           NA                 NA    NA            NA                  NA        NA
+P15   GND                           NA                 NA    NA            NA                  NA        NA
+P17   GND                           NA                 NA    NA            NA                  NA        NA
+R1    GND                           NA                 NA    NA            NA                  NA        NA
+R2    GND                           NA                 NA    NA            NA                  NA        NA
+R5    GND                           NA                 NA    NA            NA                  NA        NA
+R8    GND                           NA                 NA    NA            NA                  NA        NA
+R10   GND                           NA                 NA    NA            NA                  NA        NA
+R14   GND                           NA                 NA    NA            NA                  NA        NA
+R24   GND                           NA                 NA    NA            NA                  NA        NA
+T1    GND                           NA                 NA    NA            NA                  NA        NA
+T3    GND                           NA                 NA    NA            NA                  NA        NA
+T4    GND                           NA                 NA    NA            NA                  NA        NA
+T9    GND                           NA                 NA    NA            NA                  NA        NA
+T11   GND                           NA                 NA    NA            NA                  NA        NA
+T13   GND                           NA                 NA    NA            NA                  NA        NA
+T15   GND                           NA                 NA    NA            NA                  NA        NA
+T21   GND                           NA                 NA    NA            NA                  NA        NA
+U8    GND                           NA                 NA    NA            NA                  NA        NA
+U10   GND                           NA                 NA    NA            NA                  NA        NA
+U12   GND                           NA                 NA    NA            NA                  NA        NA
+U14   GND                           NA                 NA    NA            NA                  NA        NA
+U18   GND                           NA                 NA    NA            NA                  NA        NA
+V5    GND                           NA                 NA    NA            NA                  NA        NA
+V15   GND                           NA                 NA    NA            NA                  NA        NA
+V25   GND                           NA                 NA    NA            NA                  NA        NA
+W2    GND                           NA                 NA    NA            NA                  NA        NA
+W12   GND                           NA                 NA    NA            NA                  NA        NA
+W22   GND                           NA                 NA    NA            NA                  NA        NA
+Y9    GND                           NA                 NA    NA            NA                  NA        NA
+Y19   GND                           NA                 NA    NA            NA                  NA        NA
+J9    VCCINT                        NA                 NA    NA            NA                  NA        NA
+K8    VCCINT                        NA                 NA    NA            NA                  NA        NA
+K10   VCCINT                        NA                 NA    NA            NA                  NA        NA
+K12   VCCINT                        NA                 NA    NA            NA                  NA        NA
+K14   VCCINT                        NA                 NA    NA            NA                  NA        NA
+L9    VCCINT                        NA                 NA    NA            NA                  NA        NA
+L13   VCCINT                        NA                 NA    NA            NA                  NA        NA
+L15   VCCINT                        NA                 NA    NA            NA                  NA        NA
+M8    VCCINT                        NA                 NA    NA            NA                  NA        NA
+M14   VCCINT                        NA                 NA    NA            NA                  NA        NA
+N9    VCCINT                        NA                 NA    NA            NA                  NA        NA
+N15   VCCINT                        NA                 NA    NA            NA                  NA        NA
+P14   VCCINT                        NA                 NA    NA            NA                  NA        NA
+R15   VCCINT                        NA                 NA    NA            NA                  NA        NA
+T14   VCCINT                        NA                 NA    NA            NA                  NA        NA
+U15   VCCINT                        NA                 NA    NA            NA                  NA        NA
+T10   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+U11   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+L11   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+M10   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+P10   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+T8    VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+R9    VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+P8    VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+L7    VCCO_0                        NA                 0     NA            NA                  NA        NA
+T6    VCCO_0                        NA                 0     NA            NA                  NA        NA
+AA21  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AC25  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AD22  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AF26  VCCO_12                       NA                 12    NA            NA                  NA        NA
+U23   VCCO_12                       NA                 12    NA            NA                  NA        NA
+V20   VCCO_12                       NA                 12    NA            NA                  NA        NA
+Y24   VCCO_12                       NA                 12    NA            NA                  NA        NA
+K24   VCCO_13                       NA                 13    NA            NA                  NA        NA
+N25   VCCO_13                       NA                 13    NA            NA                  NA        NA
+P22   VCCO_13                       NA                 13    NA            NA                  NA        NA
+R19   VCCO_13                       NA                 13    NA            NA                  NA        NA
+T16   VCCO_13                       NA                 13    NA            NA                  NA        NA
+T26   VCCO_13                       NA                 13    NA            NA                  NA        NA
+A21   VCCO_14                       NA                 14    NA            NA                  NA        NA
+C25   VCCO_14                       NA                 14    NA            NA                  NA        NA
+D22   VCCO_14                       NA                 14    NA            NA                  NA        NA
+F26   VCCO_14                       NA                 14    NA            NA                  NA        NA
+G23   VCCO_14                       NA                 14    NA            NA                  NA        NA
+L21   VCCO_14                       NA                 14    NA            NA                  NA        NA
+B18   VCCO_15                       NA                 15    NA            NA                  NA        NA
+E19   VCCO_15                       NA                 15    NA            NA                  NA        NA
+F16   VCCO_15                       NA                 15    NA            NA                  NA        NA
+H20   VCCO_15                       NA                 15    NA            NA                  NA        NA
+J17   VCCO_15                       NA                 15    NA            NA                  NA        NA
+M18   VCCO_15                       NA                 15    NA            NA                  NA        NA
+A11   VCCO_16                       NA                 16    NA            NA                  NA        NA
+B8    VCCO_16                       NA                 16    NA            NA                  NA        NA
+C15   VCCO_16                       NA                 16    NA            NA                  NA        NA
+D12   VCCO_16                       NA                 16    NA            NA                  NA        NA
+E9    VCCO_16                       NA                 16    NA            NA                  NA        NA
+G13   VCCO_16                       NA                 16    NA            NA                  NA        NA
+H10   VCCO_16                       NA                 16    NA            NA                  NA        NA
+AB18  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AC15  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AE19  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AF16  VCCO_32                       NA                 32    NA            NA                  NA        NA
+W17   VCCO_32                       NA                 32    NA            NA                  NA        NA
+Y14   VCCO_32                       NA                 32    NA            NA                  NA        NA
+AA11  VCCO_33                       NA                 33    NA            NA                  NA        NA
+AB8   VCCO_33                       NA                 33    NA            NA                  NA        NA
+AD12  VCCO_33                       NA                 33    NA            NA                  NA        NA
+AE9   VCCO_33                       NA                 33    NA            NA                  NA        NA
+V10   VCCO_33                       NA                 33    NA            NA                  NA        NA
+W7    VCCO_33                       NA                 33    NA            NA                  NA        NA
+AA1   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AC5   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AD2   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AF6   VCCO_34                       NA                 34    NA            NA                  NA        NA
+U3    VCCO_34                       NA                 34    NA            NA                  NA        NA
+Y4    VCCO_34                       NA                 34    NA            NA                  NA        NA
+                                                                                                         
+Total Number of Pins Generated, 676                                                                                                   
--- a/hdl/syn/svec7_test/xc7k325tffg900pkg.txt
+++ b/hdl/syn/svec7_test/xc7k325tffg900pkg.txt
+Device/Package xc7k325tffg900 8/10/2011 13:59:07                                                                                                   
+                                                                                                         
+Pin   Pin Name                      Memory Byte Group  Bank  VCCAUX Group  Super Logic Region  I/O Type  No-Connect
+U14   DXN_0                         NA                 0     NA            NA                  CONFIG    NA
+P15   VCCADC_0                      NA                 0     NA            NA                  CONFIG    NA
+P14   GNDADC_0                      NA                 0     NA            NA                  CONFIG    NA
+U15   DXP_0                         NA                 0     NA            NA                  CONFIG    NA
+R14   VREFN_0                       NA                 0     NA            NA                  CONFIG    NA
+T15   VREFP_0                       NA                 0     NA            NA                  CONFIG    NA
+R15   VP_0                          NA                 0     NA            NA                  CONFIG    NA
+T14   VN_0                          NA                 0     NA            NA                  CONFIG    NA
+C10   VCCBATT_0                     NA                 0     NA            NA                  CONFIG    NA
+B10   CCLK_0                        NA                 0     NA            NA                  CONFIG    NA
+E10   TCK_0                         NA                 0     NA            NA                  CONFIG    NA
+F10   TMS_0                         NA                 0     NA            NA                  CONFIG    NA
+G10   TDO_0                         NA                 0     NA            NA                  CONFIG    NA
+H10   TDI_0                         NA                 0     NA            NA                  CONFIG    NA
+A10   INIT_B_0                      NA                 0     NA            NA                  CONFIG    NA
+K10   PROGRAM_B_0                   NA                 0     NA            NA                  CONFIG    NA
+L10   CFGBVS_0                      NA                 0     NA            NA                  CONFIG    NA
+M10   DONE_0                        NA                 0     NA            NA                  CONFIG    NA
+AB1   M2_0                          NA                 0     NA            NA                  CONFIG    NA
+AB5   M0_0                          NA                 0     NA            NA                  CONFIG    NA
+AB2   M1_0                          NA                 0     NA            NA                  CONFIG    NA
+Y20   IO_0_12                       NA                 12    NA            NA                  HR        NA
+Y23   IO_L1P_T0_12                  0                  12    NA            NA                  HR        NA
+Y24   IO_L1N_T0_12                  0                  12    NA            NA                  HR        NA
+Y21   IO_L2P_T0_12                  0                  12    NA            NA                  HR        NA
+AA21  IO_L2N_T0_12                  0                  12    NA            NA                  HR        NA
+AB22  IO_L3P_T0_DQS_12              0                  12    NA            NA                  HR        NA
+AB23  IO_L3N_T0_DQS_12              0                  12    NA            NA                  HR        NA
+AA22  IO_L4P_T0_12                  0                  12    NA            NA                  HR        NA
+AA23  IO_L4N_T0_12                  0                  12    NA            NA                  HR        NA
+AC20  IO_L5P_T0_12                  0                  12    NA            NA                  HR        NA
+AC21  IO_L5N_T0_12                  0                  12    NA            NA                  HR        NA
+AA20  IO_L6P_T0_12                  0                  12    NA            NA                  HR        NA
+AB20  IO_L6N_T0_VREF_12             0                  12    NA            NA                  HR        NA
+AB24  IO_L7P_T1_12                  1                  12    NA            NA                  HR        NA
+AC25  IO_L7N_T1_12                  1                  12    NA            NA                  HR        NA
+AC22  IO_L8P_T1_12                  1                  12    NA            NA                  HR        NA
+AD22  IO_L8N_T1_12                  1                  12    NA            NA                  HR        NA
+AC24  IO_L9P_T1_DQS_12              1                  12    NA            NA                  HR        NA
+AD24  IO_L9N_T1_DQS_12              1                  12    NA            NA                  HR        NA
+AD21  IO_L10P_T1_12                 1                  12    NA            NA                  HR        NA
+AE21  IO_L10N_T1_12                 1                  12    NA            NA                  HR        NA
+AE23  IO_L11P_T1_SRCC_12            1                  12    NA            NA                  HR        NA
+AF23  IO_L11N_T1_SRCC_12            1                  12    NA            NA                  HR        NA
+AD23  IO_L12P_T1_MRCC_12            1                  12    NA            NA                  HR        NA
+AE24  IO_L12N_T1_MRCC_12            1                  12    NA            NA                  HR        NA
+AF22  IO_L13P_T2_MRCC_12            2                  12    NA            NA                  HR        NA
+AG23  IO_L13N_T2_MRCC_12            2                  12    NA            NA                  HR        NA
+AG24  IO_L14P_T2_SRCC_12            2                  12    NA            NA                  HR        NA
+AH24  IO_L14N_T2_SRCC_12            2                  12    NA            NA                  HR        NA
+AJ24  IO_L15P_T2_DQS_12             2                  12    NA            NA                  HR        NA
+AK25  IO_L15N_T2_DQS_12             2                  12    NA            NA                  HR        NA
+AE25  IO_L16P_T2_12                 2                  12    NA            NA                  HR        NA
+AF25  IO_L16N_T2_12                 2                  12    NA            NA                  HR        NA
+AK23  IO_L17P_T2_12                 2                  12    NA            NA                  HR        NA
+AK24  IO_L17N_T2_12                 2                  12    NA            NA                  HR        NA
+AG25  IO_L18P_T2_12                 2                  12    NA            NA                  HR        NA
+AH25  IO_L18N_T2_12                 2                  12    NA            NA                  HR        NA
+AF20  IO_L19P_T3_12                 3                  12    NA            NA                  HR        NA
+AF21  IO_L19N_T3_VREF_12            3                  12    NA            NA                  HR        NA
+AG22  IO_L20P_T3_12                 3                  12    NA            NA                  HR        NA
+AH22  IO_L20N_T3_12                 3                  12    NA            NA                  HR        NA
+AJ22  IO_L21P_T3_DQS_12             3                  12    NA            NA                  HR        NA
+AJ23  IO_L21N_T3_DQS_12             3                  12    NA            NA                  HR        NA
+AG20  IO_L22P_T3_12                 3                  12    NA            NA                  HR        NA
+AH20  IO_L22N_T3_12                 3                  12    NA            NA                  HR        NA
+AH21  IO_L23P_T3_12                 3                  12    NA            NA                  HR        NA
+AJ21  IO_L23N_T3_12                 3                  12    NA            NA                  HR        NA
+AK20  IO_L24P_T3_12                 3                  12    NA            NA                  HR        NA
+AK21  IO_L24N_T3_12                 3                  12    NA            NA                  HR        NA
+AE20  IO_25_12                      NA                 12    NA            NA                  HR        NA
+Y25   IO_0_13                       NA                 13    NA            NA                  HR        NA
+Y26   IO_L1P_T0_13                  0                  13    NA            NA                  HR        NA
+AA26  IO_L1N_T0_13                  0                  13    NA            NA                  HR        NA
+W27   IO_L2P_T0_13                  0                  13    NA            NA                  HR        NA
+W28   IO_L2N_T0_13                  0                  13    NA            NA                  HR        NA
+Y28   IO_L3P_T0_DQS_13              0                  13    NA            NA                  HR        NA
+AA28  IO_L3N_T0_DQS_13              0                  13    NA            NA                  HR        NA
+W29   IO_L4P_T0_13                  0                  13    NA            NA                  HR        NA
+Y29   IO_L4N_T0_13                  0                  13    NA            NA                  HR        NA
+AA27  IO_L5P_T0_13                  0                  13    NA            NA                  HR        NA
+AB28  IO_L5N_T0_13                  0                  13    NA            NA                  HR        NA
+AA25  IO_L6P_T0_13                  0                  13    NA            NA                  HR        NA
+AB25  IO_L6N_T0_VREF_13             0                  13    NA            NA                  HR        NA
+AC29  IO_L7P_T1_13                  1                  13    NA            NA                  HR        NA
+AC30  IO_L7N_T1_13                  1                  13    NA            NA                  HR        NA
+Y30   IO_L8P_T1_13                  1                  13    NA            NA                  HR        NA
+AA30  IO_L8N_T1_13                  1                  13    NA            NA                  HR        NA
+AD29  IO_L9P_T1_DQS_13              1                  13    NA            NA                  HR        NA
+AE29  IO_L9N_T1_DQS_13              1                  13    NA            NA                  HR        NA
+AB29  IO_L10P_T1_13                 1                  13    NA            NA                  HR        NA
+AB30  IO_L10N_T1_13                 1                  13    NA            NA                  HR        NA
+AD27  IO_L11P_T1_SRCC_13            1                  13    NA            NA                  HR        NA
+AD28  IO_L11N_T1_SRCC_13            1                  13    NA            NA                  HR        NA
+AB27  IO_L12P_T1_MRCC_13            1                  13    NA            NA                  HR        NA
+AC27  IO_L12N_T1_MRCC_13            1                  13    NA            NA                  HR        NA
+AG29  IO_L13P_T2_MRCC_13            2                  13    NA            NA                  HR        NA
+AH29  IO_L13N_T2_MRCC_13            2                  13    NA            NA                  HR        NA
+AE28  IO_L14P_T2_SRCC_13            2                  13    NA            NA                  HR        NA
+AF28  IO_L14N_T2_SRCC_13            2                  13    NA            NA                  HR        NA
+AK29  IO_L15P_T2_DQS_13             2                  13    NA            NA                  HR        NA
+AK30  IO_L15N_T2_DQS_13             2                  13    NA            NA                  HR        NA
+AE30  IO_L16P_T2_13                 2                  13    NA            NA                  HR        NA
+AF30  IO_L16N_T2_13                 2                  13    NA            NA                  HR        NA
+AJ28  IO_L17P_T2_13                 2                  13    NA            NA                  HR        NA
+AJ29  IO_L17N_T2_13                 2                  13    NA            NA                  HR        NA
+AG30  IO_L18P_T2_13                 2                  13    NA            NA                  HR        NA
+AH30  IO_L18N_T2_13                 2                  13    NA            NA                  HR        NA
+AC26  IO_L19P_T3_13                 3                  13    NA            NA                  HR        NA
+AD26  IO_L19N_T3_VREF_13            3                  13    NA            NA                  HR        NA
+AJ27  IO_L20P_T3_13                 3                  13    NA            NA                  HR        NA
+AK28  IO_L20N_T3_13                 3                  13    NA            NA                  HR        NA
+AG27  IO_L21P_T3_DQS_13             3                  13    NA            NA                  HR        NA
+AG28  IO_L21N_T3_DQS_13             3                  13    NA            NA                  HR        NA
+AH26  IO_L22P_T3_13                 3                  13    NA            NA                  HR        NA
+AH27  IO_L22N_T3_13                 3                  13    NA            NA                  HR        NA
+AF26  IO_L23P_T3_13                 3                  13    NA            NA                  HR        NA
+AF27  IO_L23N_T3_13                 3                  13    NA            NA                  HR        NA
+AJ26  IO_L24P_T3_13                 3                  13    NA            NA                  HR        NA
+AK26  IO_L24N_T3_13                 3                  13    NA            NA                  HR        NA
+AE26  IO_25_13                      NA                 13    NA            NA                  HR        NA
+R19   IO_0_14                       NA                 14    NA            NA                  HR        NA
+P24   IO_L1P_T0_D00_MOSI_14         0                  14    NA            NA                  HR        NA
+R25   IO_L1N_T0_D01_DIN_14          0                  14    NA            NA                  HR        NA
+R20   IO_L2P_T0_D02_14              0                  14    NA            NA                  HR        NA
+R21   IO_L2N_T0_D03_14              0                  14    NA            NA                  HR        NA
+R23   IO_L3P_T0_DQS_PUDC_B_14       0                  14    NA            NA                  HR        NA
+R24   IO_L3N_T0_DQS_EMCCLK_14       0                  14    NA            NA                  HR        NA
+T20   IO_L4P_T0_D04_14              0                  14    NA            NA                  HR        NA
+T21   IO_L4N_T0_D05_14              0                  14    NA            NA                  HR        NA
+T22   IO_L5P_T0_D06_14              0                  14    NA            NA                  HR        NA
+T23   IO_L5N_T0_D07_14              0                  14    NA            NA                  HR        NA
+U19   IO_L6P_T0_FCS_B_14            0                  14    NA            NA                  HR        NA
+U20   IO_L6N_T0_D08_VREF_14         0                  14    NA            NA                  HR        NA
+P29   IO_L7P_T1_D09_14              1                  14    NA            NA                  HR        NA
+R29   IO_L7N_T1_D10_14              1                  14    NA            NA                  HR        NA
+P27   IO_L8P_T1_D11_14              1                  14    NA            NA                  HR        NA
+P28   IO_L8N_T1_D12_14              1                  14    NA            NA                  HR        NA
+R30   IO_L9P_T1_DQS_14              1                  14    NA            NA                  HR        NA
+T30   IO_L9N_T1_DQS_D13_14          1                  14    NA            NA                  HR        NA
+P26   IO_L10P_T1_D14_14             1                  14    NA            NA                  HR        NA
+R26   IO_L10N_T1_D15_14             1                  14    NA            NA                  HR        NA
+R28   IO_L11P_T1_SRCC_14            1                  14    NA            NA                  HR        NA
+T28   IO_L11N_T1_SRCC_14            1                  14    NA            NA                  HR        NA
+T26   IO_L12P_T1_MRCC_14            1                  14    NA            NA                  HR        NA
+T27   IO_L12N_T1_MRCC_14            1                  14    NA            NA                  HR        NA
+U27   IO_L13P_T2_MRCC_14            2                  14    NA            NA                  HR        NA
+U28   IO_L13N_T2_MRCC_14            2                  14    NA            NA                  HR        NA
+T25   IO_L14P_T2_SRCC_14            2                  14    NA            NA                  HR        NA
+U25   IO_L14N_T2_SRCC_14            2                  14    NA            NA                  HR        NA
+U29   IO_L15P_T2_DQS_RDWR_B_14      2                  14    NA            NA                  HR        NA
+U30   IO_L15N_T2_DQS_DOUT_CSO_B_14  2                  14    NA            NA                  HR        NA
+V26   IO_L16P_T2_CSI_B_14           2                  14    NA            NA                  HR        NA
+V27   IO_L16N_T2_A15_D31_14         2                  14    NA            NA                  HR        NA
+V29   IO_L17P_T2_A14_D30_14         2                  14    NA            NA                  HR        NA
+V30   IO_L17N_T2_A13_D29_14         2                  14    NA            NA                  HR        NA
+V25   IO_L18P_T2_A12_D28_14         2                  14    NA            NA                  HR        NA
+W26   IO_L18N_T2_A11_D27_14         2                  14    NA            NA                  HR        NA
+V19   IO_L19P_T3_A10_D26_14         3                  14    NA            NA                  HR        NA
+V20   IO_L19N_T3_A09_D25_VREF_14    3                  14    NA            NA                  HR        NA
+W23   IO_L20P_T3_A08_D24_14         3                  14    NA            NA                  HR        NA
+W24   IO_L20N_T3_A07_D23_14         3                  14    NA            NA                  HR        NA
+U22   IO_L21P_T3_DQS_14             3                  14    NA            NA                  HR        NA
+U23   IO_L21N_T3_DQS_A06_D22_14     3                  14    NA            NA                  HR        NA
+V21   IO_L22P_T3_A05_D21_14         3                  14    NA            NA                  HR        NA
+V22   IO_L22N_T3_A04_D20_14         3                  14    NA            NA                  HR        NA
+U24   IO_L23P_T3_A03_D19_14         3                  14    NA            NA                  HR        NA
+V24   IO_L23N_T3_A02_D18_14         3                  14    NA            NA                  HR        NA
+W21   IO_L24P_T3_A01_D17_14         3                  14    NA            NA                  HR        NA
+W22   IO_L24N_T3_A00_D16_14         3                  14    NA            NA                  HR        NA
+W19   IO_25_14                      NA                 14    NA            NA                  HR        NA
+M19   IO_0_15                       NA                 15    NA            NA                  HR        NA
+J23   IO_L1P_T0_AD0P_15             0                  15    NA            NA                  HR        NA
+J24   IO_L1N_T0_AD0N_15             0                  15    NA            NA                  HR        NA
+L22   IO_L2P_T0_AD8P_15             0                  15    NA            NA                  HR        NA
+L23   IO_L2N_T0_AD8N_15             0                  15    NA            NA                  HR        NA
+K23   IO_L3P_T0_DQS_AD1P_15         0                  15    NA            NA                  HR        NA
+K24   IO_L3N_T0_DQS_AD1N_15         0                  15    NA            NA                  HR        NA
+L21   IO_L4P_T0_AD9P_15             0                  15    NA            NA                  HR        NA
+K21   IO_L4N_T0_AD9N_15             0                  15    NA            NA                  HR        NA
+J21   IO_L5P_T0_AD2P_15             0                  15    NA            NA                  HR        NA
+J22   IO_L5N_T0_AD2N_15             0                  15    NA            NA                  HR        NA
+M20   IO_L6P_T0_15                  0                  15    NA            NA                  HR        NA
+L20   IO_L6N_T0_VREF_15             0                  15    NA            NA                  HR        NA
+J29   IO_L7P_T1_AD10P_15            1                  15    NA            NA                  HR        NA
+H29   IO_L7N_T1_AD10N_15            1                  15    NA            NA                  HR        NA
+J27   IO_L8P_T1_AD3P_15             1                  15    NA            NA                  HR        NA
+J28   IO_L8N_T1_AD3N_15             1                  15    NA            NA                  HR        NA
+L30   IO_L9P_T1_DQS_AD11P_15        1                  15    NA            NA                  HR        NA
+K30   IO_L9N_T1_DQS_AD11N_15        1                  15    NA            NA                  HR        NA
+K26   IO_L10P_T1_AD4P_15            1                  15    NA            NA                  HR        NA
+J26   IO_L10N_T1_AD4N_15            1                  15    NA            NA                  HR        NA
+L26   IO_L11P_T1_SRCC_AD12P_15      1                  15    NA            NA                  HR        NA
+L27   IO_L11N_T1_SRCC_AD12N_15      1                  15    NA            NA                  HR        NA
+L25   IO_L12P_T1_MRCC_AD5P_15       1                  15    NA            NA                  HR        NA
+K25   IO_L12N_T1_MRCC_AD5N_15       1                  15    NA            NA                  HR        NA
+K28   IO_L13P_T2_MRCC_15            2                  15    NA            NA                  HR        NA
+K29   IO_L13N_T2_MRCC_15            2                  15    NA            NA                  HR        NA
+M28   IO_L14P_T2_SRCC_15            2                  15    NA            NA                  HR        NA
+L28   IO_L14N_T2_SRCC_15            2                  15    NA            NA                  HR        NA
+M29   IO_L15P_T2_DQS_15             2                  15    NA            NA                  HR        NA
+M30   IO_L15N_T2_DQS_ADV_B_15       2                  15    NA            NA                  HR        NA
+N27   IO_L16P_T2_A28_15             2                  15    NA            NA                  HR        NA
+M27   IO_L16N_T2_A27_15             2                  15    NA            NA                  HR        NA
+N29   IO_L17P_T2_A26_15             2                  15    NA            NA                  HR        NA
+N30   IO_L17N_T2_A25_15             2                  15    NA            NA                  HR        NA
+N25   IO_L18P_T2_A24_15             2                  15    NA            NA                  HR        NA
+N26   IO_L18N_T2_A23_15             2                  15    NA            NA                  HR        NA
+N19   IO_L19P_T3_A22_15             3                  15    NA            NA                  HR        NA
+N20   IO_L19N_T3_A21_VREF_15        3                  15    NA            NA                  HR        NA
+N21   IO_L20P_T3_A20_15             3                  15    NA            NA                  HR        NA
+N22   IO_L20N_T3_A19_15             3                  15    NA            NA                  HR        NA
+P23   IO_L21P_T3_DQS_15             3                  15    NA            NA                  HR        NA
+N24   IO_L21N_T3_DQS_A18_15         3                  15    NA            NA                  HR        NA
+P21   IO_L22P_T3_A17_15             3                  15    NA            NA                  HR        NA
+P22   IO_L22N_T3_A16_15             3                  15    NA            NA                  HR        NA
+M24   IO_L23P_T3_FOE_B_15           3                  15    NA            NA                  HR        NA
+M25   IO_L23N_T3_FWE_B_15           3                  15    NA            NA                  HR        NA
+M22   IO_L24P_T3_RS1_15             3                  15    NA            NA                  HR        NA
+M23   IO_L24N_T3_RS0_15             3                  15    NA            NA                  HR        NA
+P19   IO_25_15                      NA                 15    NA            NA                  HR        NA
+F23   IO_0_16                       NA                 16    NA            NA                  HR        NA
+B23   IO_L1P_T0_16                  0                  16    NA            NA                  HR        NA
+A23   IO_L1N_T0_16                  0                  16    NA            NA                  HR        NA
+E23   IO_L2P_T0_16                  0                  16    NA            NA                  HR        NA
+D23   IO_L2N_T0_16                  0                  16    NA            NA                  HR        NA
+F25   IO_L3P_T0_DQS_16              0                  16    NA            NA                  HR        NA
+E25   IO_L3N_T0_DQS_16              0                  16    NA            NA                  HR        NA
+E24   IO_L4P_T0_16                  0                  16    NA            NA                  HR        NA
+D24   IO_L4N_T0_16                  0                  16    NA            NA                  HR        NA
+F26   IO_L5P_T0_16                  0                  16    NA            NA                  HR        NA
+E26   IO_L5N_T0_16                  0                  16    NA            NA                  HR        NA
+G23   IO_L6P_T0_16                  0                  16    NA            NA                  HR        NA
+G24   IO_L6N_T0_VREF_16             0                  16    NA            NA                  HR        NA
+B27   IO_L7P_T1_16                  1                  16    NA            NA                  HR        NA
+A27   IO_L7N_T1_16                  1                  16    NA            NA                  HR        NA
+C24   IO_L8P_T1_16                  1                  16    NA            NA                  HR        NA
+B24   IO_L8N_T1_16                  1                  16    NA            NA                  HR        NA
+B28   IO_L9P_T1_DQS_16              1                  16    NA            NA                  HR        NA
+A28   IO_L9N_T1_DQS_16              1                  16    NA            NA                  HR        NA
+A25   IO_L10P_T1_16                 1                  16    NA            NA                  HR        NA
+A26   IO_L10N_T1_16                 1                  16    NA            NA                  HR        NA
+D26   IO_L11P_T1_SRCC_16            1                  16    NA            NA                  HR        NA
+C26   IO_L11N_T1_SRCC_16            1                  16    NA            NA                  HR        NA
+C25   IO_L12P_T1_MRCC_16            1                  16    NA            NA                  HR        NA
+B25   IO_L12N_T1_MRCC_16            1                  16    NA            NA                  HR        NA
+D27   IO_L13P_T2_MRCC_16            2                  16    NA            NA                  HR        NA
+C27   IO_L13N_T2_MRCC_16            2                  16    NA            NA                  HR        NA
+E28   IO_L14P_T2_SRCC_16            2                  16    NA            NA                  HR        NA
+D28   IO_L14N_T2_SRCC_16            2                  16    NA            NA                  HR        NA
+C29   IO_L15P_T2_DQS_16             2                  16    NA            NA                  HR        NA
+B29   IO_L15N_T2_DQS_16             2                  16    NA            NA                  HR        NA
+D29   IO_L16P_T2_16                 2                  16    NA            NA                  HR        NA
+C30   IO_L16N_T2_16                 2                  16    NA            NA                  HR        NA
+B30   IO_L17P_T2_16                 2                  16    NA            NA                  HR        NA
+A30   IO_L17N_T2_16                 2                  16    NA            NA                  HR        NA
+E29   IO_L18P_T2_16                 2                  16    NA            NA                  HR        NA
+E30   IO_L18N_T2_16                 2                  16    NA            NA                  HR        NA
+H24   IO_L19P_T3_16                 3                  16    NA            NA                  HR        NA
+H25   IO_L19N_T3_VREF_16            3                  16    NA            NA                  HR        NA
+G28   IO_L20P_T3_16                 3                  16    NA            NA                  HR        NA
+F28   IO_L20N_T3_16                 3                  16    NA            NA                  HR        NA
+G27   IO_L21P_T3_DQS_16             3                  16    NA            NA                  HR        NA
+F27   IO_L21N_T3_DQS_16             3                  16    NA            NA                  HR        NA
+G29   IO_L22P_T3_16                 3                  16    NA            NA                  HR        NA
+F30   IO_L22N_T3_16                 3                  16    NA            NA                  HR        NA
+H26   IO_L23P_T3_16                 3                  16    NA            NA                  HR        NA
+H27   IO_L23N_T3_16                 3                  16    NA            NA                  HR        NA
+H30   IO_L24P_T3_16                 3                  16    NA            NA                  HR        NA
+G30   IO_L24N_T3_16                 3                  16    NA            NA                  HR        NA
+G25   IO_25_16                      NA                 16    NA            NA                  HR        NA
+G19   IO_0_17                       NA                 17    NA            NA                  HR        NA
+K18   IO_L1P_T0_17                  0                  17    NA            NA                  HR        NA
+J18   IO_L1N_T0_17                  0                  17    NA            NA                  HR        NA
+H20   IO_L2P_T0_17                  0                  17    NA            NA                  HR        NA
+G20   IO_L2N_T0_17                  0                  17    NA            NA                  HR        NA
+J17   IO_L3P_T0_DQS_17              0                  17    NA            NA                  HR        NA
+H17   IO_L3N_T0_DQS_17              0                  17    NA            NA                  HR        NA
+J19   IO_L4P_T0_17                  0                  17    NA            NA                  HR        NA
+H19   IO_L4N_T0_17                  0                  17    NA            NA                  HR        NA
+L17   IO_L5P_T0_17                  0                  17    NA            NA                  HR        NA
+L18   IO_L5N_T0_17                  0                  17    NA            NA                  HR        NA
+K19   IO_L6P_T0_17                  0                  17    NA            NA                  HR        NA
+K20   IO_L6N_T0_VREF_17             0                  17    NA            NA                  HR        NA
+H21   IO_L7P_T1_17                  1                  17    NA            NA                  HR        NA
+H22   IO_L7N_T1_17                  1                  17    NA            NA                  HR        NA
+D21   IO_L8P_T1_17                  1                  17    NA            NA                  HR        NA
+C21   IO_L8N_T1_17                  1                  17    NA            NA                  HR        NA
+G22   IO_L9P_T1_DQS_17              1                  17    NA            NA                  HR        NA
+F22   IO_L9N_T1_DQS_17              1                  17    NA            NA                  HR        NA
+D22   IO_L10P_T1_17                 1                  17    NA            NA                  HR        NA
+C22   IO_L10N_T1_17                 1                  17    NA            NA                  HR        NA
+F21   IO_L11P_T1_SRCC_17            1                  17    NA            NA                  HR        NA
+E21   IO_L11N_T1_SRCC_17            1                  17    NA            NA                  HR        NA
+F20   IO_L12P_T1_MRCC_17            1                  17    NA            NA                  HR        NA
+E20   IO_L12N_T1_MRCC_17            1                  17    NA            NA                  HR        NA
+D17   IO_L13P_T2_MRCC_17            2                  17    NA            NA                  HR        NA
+D18   IO_L13N_T2_MRCC_17            2                  17    NA            NA                  HR        NA
+E19   IO_L14P_T2_SRCC_17            2                  17    NA            NA                  HR        NA
+D19   IO_L14N_T2_SRCC_17            2                  17    NA            NA                  HR        NA
+D16   IO_L15P_T2_DQS_17             2                  17    NA            NA                  HR        NA
+C16   IO_L15N_T2_DQS_17             2                  17    NA            NA                  HR        NA
+G18   IO_L16P_T2_17                 2                  17    NA            NA                  HR        NA
+F18   IO_L16N_T2_17                 2                  17    NA            NA                  HR        NA
+C17   IO_L17P_T2_17                 2                  17    NA            NA                  HR        NA
+B17   IO_L17N_T2_17                 2                  17    NA            NA                  HR        NA
+G17   IO_L18P_T2_17                 2                  17    NA            NA                  HR        NA
+F17   IO_L18N_T2_17                 2                  17    NA            NA                  HR        NA
+C20   IO_L19P_T3_17                 3                  17    NA            NA                  HR        NA
+B20   IO_L19N_T3_VREF_17            3                  17    NA            NA                  HR        NA
+A16   IO_L20P_T3_17                 3                  17    NA            NA                  HR        NA
+A17   IO_L20N_T3_17                 3                  17    NA            NA                  HR        NA
+A20   IO_L21P_T3_DQS_17             3                  17    NA            NA                  HR        NA
+A21   IO_L21N_T3_DQS_17             3                  17    NA            NA                  HR        NA
+B18   IO_L22P_T3_17                 3                  17    NA            NA                  HR        NA
+A18   IO_L22N_T3_17                 3                  17    NA            NA                  HR        NA
+B22   IO_L23P_T3_17                 3                  17    NA            NA                  HR        NA
+A22   IO_L23N_T3_17                 3                  17    NA            NA                  HR        NA
+C19   IO_L24P_T3_17                 3                  17    NA            NA                  HR        NA
+B19   IO_L24N_T3_17                 3                  17    NA            NA                  HR        NA
+E18   IO_25_17                      NA                 17    NA            NA                  HR        NA
+G12   IO_0_18                       NA                 18    NA            NA                  HR        NA
+L16   IO_L1P_T0_18                  0                  18    NA            NA                  HR        NA
+K16   IO_L1N_T0_18                  0                  18    NA            NA                  HR        NA
+L15   IO_L2P_T0_18                  0                  18    NA            NA                  HR        NA
+K15   IO_L2N_T0_18                  0                  18    NA            NA                  HR        NA
+L12   IO_L3P_T0_DQS_18              0                  18    NA            NA                  HR        NA
+L13   IO_L3N_T0_DQS_18              0                  18    NA            NA                  HR        NA
+K13   IO_L4P_T0_18                  0                  18    NA            NA                  HR        NA
+J13   IO_L4N_T0_18                  0                  18    NA            NA                  HR        NA
+K14   IO_L5P_T0_18                  0                  18    NA            NA                  HR        NA
+J14   IO_L5N_T0_18                  0                  18    NA            NA                  HR        NA
+L11   IO_L6P_T0_18                  0                  18    NA            NA                  HR        NA
+K11   IO_L6N_T0_VREF_18             0                  18    NA            NA                  HR        NA
+H15   IO_L7P_T1_18                  1                  18    NA            NA                  HR        NA
+G15   IO_L7N_T1_18                  1                  18    NA            NA                  HR        NA
+J11   IO_L8P_T1_18                  1                  18    NA            NA                  HR        NA
+J12   IO_L8N_T1_18                  1                  18    NA            NA                  HR        NA
+J16   IO_L9P_T1_DQS_18              1                  18    NA            NA                  HR        NA
+H16   IO_L9N_T1_DQS_18              1                  18    NA            NA                  HR        NA
+H11   IO_L10P_T1_18                 1                  18    NA            NA                  HR        NA
+H12   IO_L10N_T1_18                 1                  18    NA            NA                  HR        NA
+H14   IO_L11P_T1_SRCC_18            1                  18    NA            NA                  HR        NA
+G14   IO_L11N_T1_SRCC_18            1                  18    NA            NA                  HR        NA
+G13   IO_L12P_T1_MRCC_18            1                  18    NA            NA                  HR        NA
+F13   IO_L12N_T1_MRCC_18            1                  18    NA            NA                  HR        NA
+D12   IO_L13P_T2_MRCC_18            2                  18    NA            NA                  HR        NA
+D13   IO_L13N_T2_MRCC_18            2                  18    NA            NA                  HR        NA
+F12   IO_L14P_T2_SRCC_18            2                  18    NA            NA                  HR        NA
+E13   IO_L14N_T2_SRCC_18            2                  18    NA            NA                  HR        NA
+C12   IO_L15P_T2_DQS_18             2                  18    NA            NA                  HR        NA
+B12   IO_L15N_T2_DQS_18             2                  18    NA            NA                  HR        NA
+F11   IO_L16P_T2_18                 2                  18    NA            NA                  HR        NA
+E11   IO_L16N_T2_18                 2                  18    NA            NA                  HR        NA
+A11   IO_L17P_T2_18                 2                  18    NA            NA                  HR        NA
+A12   IO_L17N_T2_18                 2                  18    NA            NA                  HR        NA
+D11   IO_L18P_T2_18                 2                  18    NA            NA                  HR        NA
+C11   IO_L18N_T2_18                 2                  18    NA            NA                  HR        NA
+F15   IO_L19P_T3_18                 3                  18    NA            NA                  HR        NA
+E16   IO_L19N_T3_VREF_18            3                  18    NA            NA                  HR        NA
+E14   IO_L20P_T3_18                 3                  18    NA            NA                  HR        NA
+E15   IO_L20N_T3_18                 3                  18    NA            NA                  HR        NA
+D14   IO_L21P_T3_DQS_18             3                  18    NA            NA                  HR        NA
+C14   IO_L21N_T3_DQS_18             3                  18    NA            NA                  HR        NA
+B13   IO_L22P_T3_18                 3                  18    NA            NA                  HR        NA
+A13   IO_L22N_T3_18                 3                  18    NA            NA                  HR        NA
+C15   IO_L23P_T3_18                 3                  18    NA            NA                  HR        NA
+B15   IO_L23N_T3_18                 3                  18    NA            NA                  HR        NA
+B14   IO_L24P_T3_18                 3                  18    NA            NA                  HR        NA
+A15   IO_L24N_T3_18                 3                  18    NA            NA                  HR        NA
+F16   IO_25_18                      NA                 18    NA            NA                  HR        NA
+Y14   IO_0_VRN_32                   NA                 32    0             NA                  HP        NA
+AK16  IO_L1P_T0_32                  0                  32    0             NA                  HP        NA
+AK15  IO_L1N_T0_32                  0                  32    0             NA                  HP        NA
+AG15  IO_L2P_T0_32                  0                  32    0             NA                  HP        NA
+AH15  IO_L2N_T0_32                  0                  32    0             NA                  HP        NA
+AH16  IO_L3P_T0_DQS_32              0                  32    0             NA                  HP        NA
+AJ16  IO_L3N_T0_DQS_32              0                  32    0             NA                  HP        NA
+AF15  IO_L4P_T0_32                  0                  32    0             NA                  HP        NA
+AG14  IO_L4N_T0_32                  0                  32    0             NA                  HP        NA
+AH17  IO_L5P_T0_32                  0                  32    0             NA                  HP        NA
+AJ17  IO_L5N_T0_32                  0                  32    0             NA                  HP        NA
+AE16  IO_L6P_T0_32                  0                  32    0             NA                  HP        NA
+AF16  IO_L6N_T0_VREF_32             0                  32    0             NA                  HP        NA
+AJ19  IO_L7P_T1_32                  1                  32    0             NA                  HP        NA
+AK19  IO_L7N_T1_32                  1                  32    0             NA                  HP        NA
+AG19  IO_L8P_T1_32                  1                  32    0             NA                  HP        NA
+AH19  IO_L8N_T1_32                  1                  32    0             NA                  HP        NA
+AJ18  IO_L9P_T1_DQS_32              1                  32    0             NA                  HP        NA
+AK18  IO_L9N_T1_DQS_32              1                  32    0             NA                  HP        NA
+AD19  IO_L10P_T1_32                 1                  32    0             NA                  HP        NA
+AE19  IO_L10N_T1_32                 1                  32    0             NA                  HP        NA
+AF18  IO_L11P_T1_SRCC_32            1                  32    0             NA                  HP        NA
+AG18  IO_L11N_T1_SRCC_32            1                  32    0             NA                  HP        NA
+AF17  IO_L12P_T1_MRCC_32            1                  32    0             NA                  HP        NA
+AG17  IO_L12N_T1_MRCC_32            1                  32    0             NA                  HP        NA
+AD18  IO_L13P_T2_MRCC_32            2                  32    0             NA                  HP        NA
+AE18  IO_L13N_T2_MRCC_32            2                  32    0             NA                  HP        NA
+AD17  IO_L14P_T2_SRCC_32            2                  32    0             NA                  HP        NA
+AD16  IO_L14N_T2_SRCC_32            2                  32    0             NA                  HP        NA
+Y19   IO_L15P_T2_DQS_32             2                  32    0             NA                  HP        NA
+Y18   IO_L15N_T2_DQS_32             2                  32    0             NA                  HP        NA
+AA18  IO_L16P_T2_32                 2                  32    0             NA                  HP        NA
+AB18  IO_L16N_T2_32                 2                  32    0             NA                  HP        NA
+AB19  IO_L17P_T2_32                 2                  32    0             NA                  HP        NA
+AC19  IO_L17N_T2_32                 2                  32    0             NA                  HP        NA
+AB17  IO_L18P_T2_32                 2                  32    0             NA                  HP        NA
+AC17  IO_L18N_T2_32                 2                  32    0             NA                  HP        NA
+AE15  IO_L19P_T3_32                 3                  32    0             NA                  HP        NA
+AE14  IO_L19N_T3_VREF_32            3                  32    0             NA                  HP        NA
+AA15  IO_L20P_T3_32                 3                  32    0             NA                  HP        NA
+AB15  IO_L20N_T3_32                 3                  32    0             NA                  HP        NA
+AC16  IO_L21P_T3_DQS_32             3                  32    0             NA                  HP        NA
+AC15  IO_L21N_T3_DQS_32             3                  32    0             NA                  HP        NA
+AC14  IO_L22P_T3_32                 3                  32    0             NA                  HP        NA
+AD14  IO_L22N_T3_32                 3                  32    0             NA                  HP        NA
+AA17  IO_L23P_T3_32                 3                  32    0             NA                  HP        NA
+AA16  IO_L23N_T3_32                 3                  32    0             NA                  HP        NA
+Y16   IO_L24P_T3_32                 3                  32    0             NA                  HP        NA
+Y15   IO_L24N_T3_32                 3                  32    0             NA                  HP        NA
+AB14  IO_25_VRP_32                  NA                 32    0             NA                  HP        NA
+Y13   IO_0_VRN_33                   NA                 33    0             NA                  HP        NA
+AA12  IO_L1P_T0_33                  0                  33    0             NA                  HP        NA
+AB12  IO_L1N_T0_33                  0                  33    0             NA                  HP        NA
+AA8   IO_L2P_T0_33                  0                  33    0             NA                  HP        NA
+AB8   IO_L2N_T0_33                  0                  33    0             NA                  HP        NA
+AB9   IO_L3P_T0_DQS_33              0                  33    0             NA                  HP        NA
+AC9   IO_L3N_T0_DQS_33              0                  33    0             NA                  HP        NA
+Y11   IO_L4P_T0_33                  0                  33    0             NA                  HP        NA
+Y10   IO_L4N_T0_33                  0                  33    0             NA                  HP        NA
+AA11  IO_L5P_T0_33                  0                  33    0             NA                  HP        NA
+AA10  IO_L5N_T0_33                  0                  33    0             NA                  HP        NA
+AA13  IO_L6P_T0_33                  0                  33    0             NA                  HP        NA
+AB13  IO_L6N_T0_VREF_33             0                  33    0             NA                  HP        NA
+AB10  IO_L7P_T1_33                  1                  33    0             NA                  HP        NA
+AC10  IO_L7N_T1_33                  1                  33    0             NA                  HP        NA
+AD8   IO_L8P_T1_33                  1                  33    0             NA                  HP        NA
+AE8   IO_L8N_T1_33                  1                  33    0             NA                  HP        NA
+AC12  IO_L9P_T1_DQS_33              1                  33    0             NA                  HP        NA
+AC11  IO_L9N_T1_DQS_33              1                  33    0             NA                  HP        NA
+AD9   IO_L10P_T1_33                 1                  33    0             NA                  HP        NA
+AE9   IO_L10N_T1_33                 1                  33    0             NA                  HP        NA
+AE11  IO_L11P_T1_SRCC_33            1                  33    0             NA                  HP        NA
+AF11  IO_L11N_T1_SRCC_33            1                  33    0             NA                  HP        NA
+AD12  IO_L12P_T1_MRCC_33            1                  33    0             NA                  HP        NA
+AD11  IO_L12N_T1_MRCC_33            1                  33    0             NA                  HP        NA
+AG10  IO_L13P_T2_MRCC_33            2                  33    0             NA                  HP        NA
+AH10  IO_L13N_T2_MRCC_33            2                  33    0             NA                  HP        NA
+AE10  IO_L14P_T2_SRCC_33            2                  33    0             NA                  HP        NA
+AF10  IO_L14N_T2_SRCC_33            2                  33    0             NA                  HP        NA
+AJ9   IO_L15P_T2_DQS_33             2                  33    0             NA                  HP        NA
+AK9   IO_L15N_T2_DQS_33             2                  33    0             NA                  HP        NA
+AG9   IO_L16P_T2_33                 2                  33    0             NA                  HP        NA
+AH9   IO_L16N_T2_33                 2                  33    0             NA                  HP        NA
+AK11  IO_L17P_T2_33                 2                  33    0             NA                  HP        NA
+AK10  IO_L17N_T2_33                 2                  33    0             NA                  HP        NA
+AH11  IO_L18P_T2_33                 2                  33    0             NA                  HP        NA
+AJ11  IO_L18N_T2_33                 2                  33    0             NA                  HP        NA
+AE13  IO_L19P_T3_33                 3                  33    0             NA                  HP        NA
+AF13  IO_L19N_T3_VREF_33            3                  33    0             NA                  HP        NA
+AK14  IO_L20P_T3_33                 3                  33    0             NA                  HP        NA
+AK13  IO_L20N_T3_33                 3                  33    0             NA                  HP        NA
+AH14  IO_L21P_T3_DQS_33             3                  33    0             NA                  HP        NA
+AJ14  IO_L21N_T3_DQS_33             3                  33    0             NA                  HP        NA
+AJ13  IO_L22P_T3_33                 3                  33    0             NA                  HP        NA
+AJ12  IO_L22N_T3_33                 3                  33    0             NA                  HP        NA
+AF12  IO_L23P_T3_33                 3                  33    0             NA                  HP        NA
+AG12  IO_L23N_T3_33                 3                  33    0             NA                  HP        NA
+AG13  IO_L24P_T3_33                 3                  33    0             NA                  HP        NA
+AH12  IO_L24N_T3_33                 3                  33    0             NA                  HP        NA
+AD13  IO_25_VRP_33                  NA                 33    0             NA                  HP        NA
+AC6   IO_0_VRN_34                   NA                 34    0             NA                  HP        NA
+AD4   IO_L1P_T0_34                  0                  34    0             NA                  HP        NA
+AD3   IO_L1N_T0_34                  0                  34    0             NA                  HP        NA
+AC2   IO_L2P_T0_34                  0                  34    0             NA                  HP        NA
+AC1   IO_L2N_T0_34                  0                  34    0             NA                  HP        NA
+AD2   IO_L3P_T0_DQS_34              0                  34    0             NA                  HP        NA
+AD1   IO_L3N_T0_DQS_34              0                  34    0             NA                  HP        NA
+AC5   IO_L4P_T0_34                  0                  34    0             NA                  HP        NA
+AC4   IO_L4N_T0_34                  0                  34    0             NA                  HP        NA
+AD6   IO_L5P_T0_34                  0                  34    0             NA                  HP        NA
+AE6   IO_L5N_T0_34                  0                  34    0             NA                  HP        NA
+AC7   IO_L6P_T0_34                  0                  34    0             NA                  HP        NA
+AD7   IO_L6N_T0_VREF_34             0                  34    0             NA                  HP        NA
+AF3   IO_L7P_T1_34                  1                  34    0             NA                  HP        NA
+AF2   IO_L7N_T1_34                  1                  34    0             NA                  HP        NA
+AE1   IO_L8P_T1_34                  1                  34    0             NA                  HP        NA
+AF1   IO_L8N_T1_34                  1                  34    0             NA                  HP        NA
+AG4   IO_L9P_T1_DQS_34              1                  34    0             NA                  HP        NA
+AG3   IO_L9N_T1_DQS_34              1                  34    0             NA                  HP        NA
+AE4   IO_L10P_T1_34                 1                  34    0             NA                  HP        NA
+AE3   IO_L10N_T1_34                 1                  34    0             NA                  HP        NA
+AE5   IO_L11P_T1_SRCC_34            1                  34    0             NA                  HP        NA
+AF5   IO_L11N_T1_SRCC_34            1                  34    0             NA                  HP        NA
+AF6   IO_L12P_T1_MRCC_34            1                  34    0             NA                  HP        NA
+AG5   IO_L12N_T1_MRCC_34            1                  34    0             NA                  HP        NA
+AH4   IO_L13P_T2_MRCC_34            2                  34    0             NA                  HP        NA
+AJ4   IO_L13N_T2_MRCC_34            2                  34    0             NA                  HP        NA
+AH6   IO_L14P_T2_SRCC_34            2                  34    0             NA                  HP        NA
+AH5   IO_L14N_T2_SRCC_34            2                  34    0             NA                  HP        NA
+AG2   IO_L15P_T2_DQS_34             2                  34    0             NA                  HP        NA
+AH1   IO_L15N_T2_DQS_34             2                  34    0             NA                  HP        NA
+AH2   IO_L16P_T2_34                 2                  34    0             NA                  HP        NA
+AJ2   IO_L16N_T2_34                 2                  34    0             NA                  HP        NA
+AJ1   IO_L17P_T2_34                 2                  34    0             NA                  HP        NA
+AK1   IO_L17N_T2_34                 2                  34    0             NA                  HP        NA
+AJ3   IO_L18P_T2_34                 2                  34    0             NA                  HP        NA
+AK3   IO_L18N_T2_34                 2                  34    0             NA                  HP        NA
+AF8   IO_L19P_T3_34                 3                  34    0             NA                  HP        NA
+AG8   IO_L19N_T3_VREF_34            3                  34    0             NA                  HP        NA
+AF7   IO_L20P_T3_34                 3                  34    0             NA                  HP        NA
+AG7   IO_L20N_T3_34                 3                  34    0             NA                  HP        NA
+AH7   IO_L21P_T3_DQS_34             3                  34    0             NA                  HP        NA
+AJ7   IO_L21N_T3_DQS_34             3                  34    0             NA                  HP        NA
+AJ6   IO_L22P_T3_34                 3                  34    0             NA                  HP        NA
+AK6   IO_L22N_T3_34                 3                  34    0             NA                  HP        NA
+AJ8   IO_L23P_T3_34                 3                  34    0             NA                  HP        NA
+AK8   IO_L23N_T3_34                 3                  34    0             NA                  HP        NA
+AK5   IO_L24P_T3_34                 3                  34    0             NA                  HP        NA
+AK4   IO_L24N_T3_34                 3                  34    0             NA                  HP        NA
+AB7   IO_25_VRP_34                  NA                 34    0             NA                  HP        NA
+T2    MGTXTXP3_115                  NA                 115   NA            NA                  GTX       NA
+V6    MGTXRXP3_115                  NA                 115   NA            NA                  GTX       NA
+T1    MGTXTXN3_115                  NA                 115   NA            NA                  GTX       NA
+V5    MGTXRXN3_115                  NA                 115   NA            NA                  GTX       NA
+U4    MGTXTXP2_115                  NA                 115   NA            NA                  GTX       NA
+W4    MGTXRXP2_115                  NA                 115   NA            NA                  GTX       NA
+U3    MGTXTXN2_115                  NA                 115   NA            NA                  GTX       NA
+R8    MGTREFCLK0P_115               NA                 115   NA            NA                  GTX       NA
+W3    MGTXRXN2_115                  NA                 115   NA            NA                  GTX       NA
+W7    MGTAVTTRCAL_115               NA                 115   NA            NA                  GTX       NA
+R7    MGTREFCLK0N_115               NA                 115   NA            NA                  GTX       NA
+W8    MGTRREF_115                   NA                 115   NA            NA                  GTX       NA
+U7    MGTREFCLK1N_115               NA                 115   NA            NA                  GTX       NA
+U8    MGTREFCLK1P_115               NA                 115   NA            NA                  GTX       NA
+V2    MGTXTXP1_115                  NA                 115   NA            NA                  GTX       NA
+Y6    MGTXRXP1_115                  NA                 115   NA            NA                  GTX       NA
+V1    MGTXTXN1_115                  NA                 115   NA            NA                  GTX       NA
+Y5    MGTXRXN1_115                  NA                 115   NA            NA                  GTX       NA
+Y2    MGTXTXP0_115                  NA                 115   NA            NA                  GTX       NA
+AA4   MGTXRXP0_115                  NA                 115   NA            NA                  GTX       NA
+Y1    MGTXTXN0_115                  NA                 115   NA            NA                  GTX       NA
+AA3   MGTXRXN0_115                  NA                 115   NA            NA                  GTX       NA
+L4    MGTXTXP3_116                  NA                 116   NA            NA                  GTX       NA
+M6    MGTXRXP3_116                  NA                 116   NA            NA                  GTX       NA
+L3    MGTXTXN3_116                  NA                 116   NA            NA                  GTX       NA
+M5    MGTXRXN3_116                  NA                 116   NA            NA                  GTX       NA
+M2    MGTXTXP2_116                  NA                 116   NA            NA                  GTX       NA
+P6    MGTXRXP2_116                  NA                 116   NA            NA                  GTX       NA
+M1    MGTXTXN2_116                  NA                 116   NA            NA                  GTX       NA
+L8    MGTREFCLK0P_116               NA                 116   NA            NA                  GTX       NA
+P5    MGTXRXN2_116                  NA                 116   NA            NA                  GTX       NA
+L7    MGTREFCLK0N_116               NA                 116   NA            NA                  GTX       NA
+N7    MGTREFCLK1N_116               NA                 116   NA            NA                  GTX       NA
+N8    MGTREFCLK1P_116               NA                 116   NA            NA                  GTX       NA
+N4    MGTXTXP1_116                  NA                 116   NA            NA                  GTX       NA
+R4    MGTXRXP1_116                  NA                 116   NA            NA                  GTX       NA
+N3    MGTXTXN1_116                  NA                 116   NA            NA                  GTX       NA
+R3    MGTXRXN1_116                  NA                 116   NA            NA                  GTX       NA
+P2    MGTXTXP0_116                  NA                 116   NA            NA                  GTX       NA
+T6    MGTXRXP0_116                  NA                 116   NA            NA                  GTX       NA
+P1    MGTXTXN0_116                  NA                 116   NA            NA                  GTX       NA
+T5    MGTXRXN0_116                  NA                 116   NA            NA                  GTX       NA
+F2    MGTXTXP3_117                  NA                 117   NA            NA                  GTX       NA
+F6    MGTXRXP3_117                  NA                 117   NA            NA                  GTX       NA
+F1    MGTXTXN3_117                  NA                 117   NA            NA                  GTX       NA
+F5    MGTXRXN3_117                  NA                 117   NA            NA                  GTX       NA
+H2    MGTXTXP2_117                  NA                 117   NA            NA                  GTX       NA
+G4    MGTXRXP2_117                  NA                 117   NA            NA                  GTX       NA
+H1    MGTXTXN2_117                  NA                 117   NA            NA                  GTX       NA
+G8    MGTREFCLK0P_117               NA                 117   NA            NA                  GTX       NA
+G3    MGTXRXN2_117                  NA                 117   NA            NA                  GTX       NA
+G7    MGTREFCLK0N_117               NA                 117   NA            NA                  GTX       NA
+J7    MGTREFCLK1N_117               NA                 117   NA            NA                  GTX       NA
+J8    MGTREFCLK1P_117               NA                 117   NA            NA                  GTX       NA
+J4    MGTXTXP1_117                  NA                 117   NA            NA                  GTX       NA
+H6    MGTXRXP1_117                  NA                 117   NA            NA                  GTX       NA
+J3    MGTXTXN1_117                  NA                 117   NA            NA                  GTX       NA
+H5    MGTXRXN1_117                  NA                 117   NA            NA                  GTX       NA
+K2    MGTXTXP0_117                  NA                 117   NA            NA                  GTX       NA
+K6    MGTXRXP0_117                  NA                 117   NA            NA                  GTX       NA
+K1    MGTXTXN0_117                  NA                 117   NA            NA                  GTX       NA
+K5    MGTXRXN0_117                  NA                 117   NA            NA                  GTX       NA
+A4    MGTXTXP3_118                  NA                 118   NA            NA                  GTX       NA
+A8    MGTXRXP3_118                  NA                 118   NA            NA                  GTX       NA
+A3    MGTXTXN3_118                  NA                 118   NA            NA                  GTX       NA
+A7    MGTXRXN3_118                  NA                 118   NA            NA                  GTX       NA
+B2    MGTXTXP2_118                  NA                 118   NA            NA                  GTX       NA
+B6    MGTXRXP2_118                  NA                 118   NA            NA                  GTX       NA
+B1    MGTXTXN2_118                  NA                 118   NA            NA                  GTX       NA
+C8    MGTREFCLK0P_118               NA                 118   NA            NA                  GTX       NA
+B5    MGTXRXN2_118                  NA                 118   NA            NA                  GTX       NA
+C7    MGTREFCLK0N_118               NA                 118   NA            NA                  GTX       NA
+E7    MGTREFCLK1N_118               NA                 118   NA            NA                  GTX       NA
+E8    MGTREFCLK1P_118               NA                 118   NA            NA                  GTX       NA
+C4    MGTXTXP1_118                  NA                 118   NA            NA                  GTX       NA
+D6    MGTXRXP1_118                  NA                 118   NA            NA                  GTX       NA
+C3    MGTXTXN1_118                  NA                 118   NA            NA                  GTX       NA
+D5    MGTXRXN1_118                  NA                 118   NA            NA                  GTX       NA
+D2    MGTXTXP0_118                  NA                 118   NA            NA                  GTX       NA
+E4    MGTXRXP0_118                  NA                 118   NA            NA                  GTX       NA
+D1    MGTXTXN0_118                  NA                 118   NA            NA                  GTX       NA
+E3    MGTXRXN0_118                  NA                 118   NA            NA                  GTX       NA
+B7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+D7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+F7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+H7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+K7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+M7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+P7    MGTAVCC                       NA                 NA    NA            NA                  NA        NA
+T7    MGTVCCAUX                     NA                 NA    NA            NA                  NA        NA
+V7    MGTVCCAUX                     NA                 NA    NA            NA                  NA        NA
+B3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+C5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+D3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+E5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+F3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+G5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+H3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+J5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+K3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+L5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+M3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+N5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+P3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+R5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+T3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+U5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+V3    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+W5    MGTAVTT                       NA                 NA    NA            NA                  NA        NA
+N16   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+R16   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+U16   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+W16   VCCBRAM                       NA                 NA    NA            NA                  NA        NA
+A1    GND                           NA                 NA    NA            NA                  NA        NA
+A14   GND                           NA                 NA    NA            NA                  NA        NA
+A2    GND                           NA                 NA    NA            NA                  NA        NA
+A24   GND                           NA                 NA    NA            NA                  NA        NA
+A5    GND                           NA                 NA    NA            NA                  NA        NA
+A6    GND                           NA                 NA    NA            NA                  NA        NA
+A9    GND                           NA                 NA    NA            NA                  NA        NA
+AA1   GND                           NA                 NA    NA            NA                  NA        NA
+AA14  GND                           NA                 NA    NA            NA                  NA        NA
+AA2   GND                           NA                 NA    NA            NA                  NA        NA
+AA24  GND                           NA                 NA    NA            NA                  NA        NA
+AA5   GND                           NA                 NA    NA            NA                  NA        NA
+AA6   GND                           NA                 NA    NA            NA                  NA        NA
+AA7   GND                           NA                 NA    NA            NA                  NA        NA
+AB11  GND                           NA                 NA    NA            NA                  NA        NA
+AB21  GND                           NA                 NA    NA            NA                  NA        NA
+AB3   GND                           NA                 NA    NA            NA                  NA        NA
+AB4   GND                           NA                 NA    NA            NA                  NA        NA
+AC18  GND                           NA                 NA    NA            NA                  NA        NA
+AC28  GND                           NA                 NA    NA            NA                  NA        NA
+AC8   GND                           NA                 NA    NA            NA                  NA        NA
+AD15  GND                           NA                 NA    NA            NA                  NA        NA
+AD25  GND                           NA                 NA    NA            NA                  NA        NA
+AD5   GND                           NA                 NA    NA            NA                  NA        NA
+AE12  GND                           NA                 NA    NA            NA                  NA        NA
+AE2   GND                           NA                 NA    NA            NA                  NA        NA
+AE22  GND                           NA                 NA    NA            NA                  NA        NA
+AF19  GND                           NA                 NA    NA            NA                  NA        NA
+AF29  GND                           NA                 NA    NA            NA                  NA        NA
+AF9   GND                           NA                 NA    NA            NA                  NA        NA
+AG16  GND                           NA                 NA    NA            NA                  NA        NA
+AG26  GND                           NA                 NA    NA            NA                  NA        NA
+AG6   GND                           NA                 NA    NA            NA                  NA        NA
+AH13  GND                           NA                 NA    NA            NA                  NA        NA
+AH23  GND                           NA                 NA    NA            NA                  NA        NA
+AH3   GND                           NA                 NA    NA            NA                  NA        NA
+AJ10  GND                           NA                 NA    NA            NA                  NA        NA
+AJ20  GND                           NA                 NA    NA            NA                  NA        NA
+AJ30  GND                           NA                 NA    NA            NA                  NA        NA
+AK17  GND                           NA                 NA    NA            NA                  NA        NA
+AK27  GND                           NA                 NA    NA            NA                  NA        NA
+AK7   GND                           NA                 NA    NA            NA                  NA        NA
+B11   GND                           NA                 NA    NA            NA                  NA        NA
+B21   GND                           NA                 NA    NA            NA                  NA        NA
+B4    GND                           NA                 NA    NA            NA                  NA        NA
+B8    GND                           NA                 NA    NA            NA                  NA        NA
+B9    GND                           NA                 NA    NA            NA                  NA        NA
+C1    GND                           NA                 NA    NA            NA                  NA        NA
+C18   GND                           NA                 NA    NA            NA                  NA        NA
+C2    GND                           NA                 NA    NA            NA                  NA        NA
+C28   GND                           NA                 NA    NA            NA                  NA        NA
+C6    GND                           NA                 NA    NA            NA                  NA        NA
+C9    GND                           NA                 NA    NA            NA                  NA        NA
+D15   GND                           NA                 NA    NA            NA                  NA        NA
+D25   GND                           NA                 NA    NA            NA                  NA        NA
+D4    GND                           NA                 NA    NA            NA                  NA        NA
+D8    GND                           NA                 NA    NA            NA                  NA        NA
+D9    GND                           NA                 NA    NA            NA                  NA        NA
+E1    GND                           NA                 NA    NA            NA                  NA        NA
+E12   GND                           NA                 NA    NA            NA                  NA        NA
+E2    GND                           NA                 NA    NA            NA                  NA        NA
+E22   GND                           NA                 NA    NA            NA                  NA        NA
+E6    GND                           NA                 NA    NA            NA                  NA        NA
+E9    GND                           NA                 NA    NA            NA                  NA        NA
+F19   GND                           NA                 NA    NA            NA                  NA        NA
+F29   GND                           NA                 NA    NA            NA                  NA        NA
+F4    GND                           NA                 NA    NA            NA                  NA        NA
+F8    GND                           NA                 NA    NA            NA                  NA        NA
+F9    GND                           NA                 NA    NA            NA                  NA        NA
+G1    GND                           NA                 NA    NA            NA                  NA        NA
+G16   GND                           NA                 NA    NA            NA                  NA        NA
+G2    GND                           NA                 NA    NA            NA                  NA        NA
+G26   GND                           NA                 NA    NA            NA                  NA        NA
+G6    GND                           NA                 NA    NA            NA                  NA        NA
+G9    GND                           NA                 NA    NA            NA                  NA        NA
+H13   GND                           NA                 NA    NA            NA                  NA        NA
+H23   GND                           NA                 NA    NA            NA                  NA        NA
+H4    GND                           NA                 NA    NA            NA                  NA        NA
+H8    GND                           NA                 NA    NA            NA                  NA        NA
+H9    GND                           NA                 NA    NA            NA                  NA        NA
+J1    GND                           NA                 NA    NA            NA                  NA        NA
+J10   GND                           NA                 NA    NA            NA                  NA        NA
+J2    GND                           NA                 NA    NA            NA                  NA        NA
+J20   GND                           NA                 NA    NA            NA                  NA        NA
+J30   GND                           NA                 NA    NA            NA                  NA        NA
+J6    GND                           NA                 NA    NA            NA                  NA        NA
+J9    GND                           NA                 NA    NA            NA                  NA        NA
+K17   GND                           NA                 NA    NA            NA                  NA        NA
+K27   GND                           NA                 NA    NA            NA                  NA        NA
+K4    GND                           NA                 NA    NA            NA                  NA        NA
+K8    GND                           NA                 NA    NA            NA                  NA        NA
+K9    GND                           NA                 NA    NA            NA                  NA        NA
+L1    GND                           NA                 NA    NA            NA                  NA        NA
+L14   GND                           NA                 NA    NA            NA                  NA        NA
+L2    GND                           NA                 NA    NA            NA                  NA        NA
+L24   GND                           NA                 NA    NA            NA                  NA        NA
+L6    GND                           NA                 NA    NA            NA                  NA        NA
+L9    GND                           NA                 NA    NA            NA                  NA        NA
+M12   GND                           NA                 NA    NA            NA                  NA        NA
+M14   GND                           NA                 NA    NA            NA                  NA        NA
+M16   GND                           NA                 NA    NA            NA                  NA        NA
+M18   GND                           NA                 NA    NA            NA                  NA        NA
+M21   GND                           NA                 NA    NA            NA                  NA        NA
+M4    GND                           NA                 NA    NA            NA                  NA        NA
+M8    GND                           NA                 NA    NA            NA                  NA        NA
+M9    GND                           NA                 NA    NA            NA                  NA        NA
+N1    GND                           NA                 NA    NA            NA                  NA        NA
+N11   GND                           NA                 NA    NA            NA                  NA        NA
+N13   GND                           NA                 NA    NA            NA                  NA        NA
+N15   GND                           NA                 NA    NA            NA                  NA        NA
+N17   GND                           NA                 NA    NA            NA                  NA        NA
+N2    GND                           NA                 NA    NA            NA                  NA        NA
+N28   GND                           NA                 NA    NA            NA                  NA        NA
+N6    GND                           NA                 NA    NA            NA                  NA        NA
+N9    GND                           NA                 NA    NA            NA                  NA        NA
+P10   GND                           NA                 NA    NA            NA                  NA        NA
+P12   GND                           NA                 NA    NA            NA                  NA        NA
+P16   GND                           NA                 NA    NA            NA                  NA        NA
+P18   GND                           NA                 NA    NA            NA                  NA        NA
+P25   GND                           NA                 NA    NA            NA                  NA        NA
+P4    GND                           NA                 NA    NA            NA                  NA        NA
+P8    GND                           NA                 NA    NA            NA                  NA        NA
+P9    GND                           NA                 NA    NA            NA                  NA        NA
+R1    GND                           NA                 NA    NA            NA                  NA        NA
+R11   GND                           NA                 NA    NA            NA                  NA        NA
+R13   GND                           NA                 NA    NA            NA                  NA        NA
+R17   GND                           NA                 NA    NA            NA                  NA        NA
+R2    GND                           NA                 NA    NA            NA                  NA        NA
+R22   GND                           NA                 NA    NA            NA                  NA        NA
+R6    GND                           NA                 NA    NA            NA                  NA        NA
+R9    GND                           NA                 NA    NA            NA                  NA        NA
+T10   GND                           NA                 NA    NA            NA                  NA        NA
+T12   GND                           NA                 NA    NA            NA                  NA        NA
+T16   GND                           NA                 NA    NA            NA                  NA        NA
+T18   GND                           NA                 NA    NA            NA                  NA        NA
+T19   GND                           NA                 NA    NA            NA                  NA        NA
+T29   GND                           NA                 NA    NA            NA                  NA        NA
+T4    GND                           NA                 NA    NA            NA                  NA        NA
+T8    GND                           NA                 NA    NA            NA                  NA        NA
+U1    GND                           NA                 NA    NA            NA                  NA        NA
+U11   GND                           NA                 NA    NA            NA                  NA        NA
+U13   GND                           NA                 NA    NA            NA                  NA        NA
+U17   GND                           NA                 NA    NA            NA                  NA        NA
+U2    GND                           NA                 NA    NA            NA                  NA        NA
+U26   GND                           NA                 NA    NA            NA                  NA        NA
+U6    GND                           NA                 NA    NA            NA                  NA        NA
+U9    GND                           NA                 NA    NA            NA                  NA        NA
+V10   GND                           NA                 NA    NA            NA                  NA        NA
+V12   GND                           NA                 NA    NA            NA                  NA        NA
+V14   GND                           NA                 NA    NA            NA                  NA        NA
+V16   GND                           NA                 NA    NA            NA                  NA        NA
+V18   GND                           NA                 NA    NA            NA                  NA        NA
+V23   GND                           NA                 NA    NA            NA                  NA        NA
+V4    GND                           NA                 NA    NA            NA                  NA        NA
+V8    GND                           NA                 NA    NA            NA                  NA        NA
+V9    GND                           NA                 NA    NA            NA                  NA        NA
+W1    GND                           NA                 NA    NA            NA                  NA        NA
+W11   GND                           NA                 NA    NA            NA                  NA        NA
+W13   GND                           NA                 NA    NA            NA                  NA        NA
+W15   GND                           NA                 NA    NA            NA                  NA        NA
+W17   GND                           NA                 NA    NA            NA                  NA        NA
+W2    GND                           NA                 NA    NA            NA                  NA        NA
+W20   GND                           NA                 NA    NA            NA                  NA        NA
+W30   GND                           NA                 NA    NA            NA                  NA        NA
+W6    GND                           NA                 NA    NA            NA                  NA        NA
+W9    GND                           NA                 NA    NA            NA                  NA        NA
+Y17   GND                           NA                 NA    NA            NA                  NA        NA
+Y27   GND                           NA                 NA    NA            NA                  NA        NA
+Y3    GND                           NA                 NA    NA            NA                  NA        NA
+Y4    GND                           NA                 NA    NA            NA                  NA        NA
+Y7    GND                           NA                 NA    NA            NA                  NA        NA
+Y8    GND                           NA                 NA    NA            NA                  NA        NA
+Y9    GND                           NA                 NA    NA            NA                  NA        NA
+M11   VCCINT                        NA                 NA    NA            NA                  NA        NA
+M13   VCCINT                        NA                 NA    NA            NA                  NA        NA
+M15   VCCINT                        NA                 NA    NA            NA                  NA        NA
+M17   VCCINT                        NA                 NA    NA            NA                  NA        NA
+N10   VCCINT                        NA                 NA    NA            NA                  NA        NA
+N12   VCCINT                        NA                 NA    NA            NA                  NA        NA
+N14   VCCINT                        NA                 NA    NA            NA                  NA        NA
+N18   VCCINT                        NA                 NA    NA            NA                  NA        NA
+P11   VCCINT                        NA                 NA    NA            NA                  NA        NA
+P17   VCCINT                        NA                 NA    NA            NA                  NA        NA
+R10   VCCINT                        NA                 NA    NA            NA                  NA        NA
+R12   VCCINT                        NA                 NA    NA            NA                  NA        NA
+R18   VCCINT                        NA                 NA    NA            NA                  NA        NA
+T11   VCCINT                        NA                 NA    NA            NA                  NA        NA
+T17   VCCINT                        NA                 NA    NA            NA                  NA        NA
+U10   VCCINT                        NA                 NA    NA            NA                  NA        NA
+U12   VCCINT                        NA                 NA    NA            NA                  NA        NA
+U18   VCCINT                        NA                 NA    NA            NA                  NA        NA
+V17   VCCINT                        NA                 NA    NA            NA                  NA        NA
+W18   VCCINT                        NA                 NA    NA            NA                  NA        NA
+P13   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+T13   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+V13   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+V15   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+W14   VCCAUX                        NA                 NA    NA            NA                  NA        NA
+W12   VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+V11   VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+W10   VCCAUX_IO_G0                  NA                 NA    NA            NA                  NA        NA
+AA19  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AB16  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AE17  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AF14  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AH18  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AJ15  VCCO_32                       NA                 32    NA            NA                  NA        NA
+AA9   VCCO_33                       NA                 33    NA            NA                  NA        NA
+AC13  VCCO_33                       NA                 33    NA            NA                  NA        NA
+AD10  VCCO_33                       NA                 33    NA            NA                  NA        NA
+AG11  VCCO_33                       NA                 33    NA            NA                  NA        NA
+AK12  VCCO_33                       NA                 33    NA            NA                  NA        NA
+Y12   VCCO_33                       NA                 33    NA            NA                  NA        NA
+AC3   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AE7   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AF4   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AG1   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AH8   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AJ5   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AK2   VCCO_34                       NA                 34    NA            NA                  NA        NA
+AC23  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AD20  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AF24  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AG21  VCCO_12                       NA                 12    NA            NA                  NA        NA
+AK22  VCCO_12                       NA                 12    NA            NA                  NA        NA
+Y22   VCCO_12                       NA                 12    NA            NA                  NA        NA
+AA29  VCCO_13                       NA                 13    NA            NA                  NA        NA
+AB26  VCCO_13                       NA                 13    NA            NA                  NA        NA
+AD30  VCCO_13                       NA                 13    NA            NA                  NA        NA
+AE27  VCCO_13                       NA                 13    NA            NA                  NA        NA
+AH28  VCCO_13                       NA                 13    NA            NA                  NA        NA
+AJ25  VCCO_13                       NA                 13    NA            NA                  NA        NA
+P30   VCCO_14                       NA                 14    NA            NA                  NA        NA
+R27   VCCO_14                       NA                 14    NA            NA                  NA        NA
+T24   VCCO_14                       NA                 14    NA            NA                  NA        NA
+U21   VCCO_14                       NA                 14    NA            NA                  NA        NA
+V28   VCCO_14                       NA                 14    NA            NA                  NA        NA
+W25   VCCO_14                       NA                 14    NA            NA                  NA        NA
+J25   VCCO_15                       NA                 15    NA            NA                  NA        NA
+K22   VCCO_15                       NA                 15    NA            NA                  NA        NA
+L29   VCCO_15                       NA                 15    NA            NA                  NA        NA
+M26   VCCO_15                       NA                 15    NA            NA                  NA        NA
+N23   VCCO_15                       NA                 15    NA            NA                  NA        NA
+P20   VCCO_15                       NA                 15    NA            NA                  NA        NA
+A29   VCCO_16                       NA                 16    NA            NA                  NA        NA
+B26   VCCO_16                       NA                 16    NA            NA                  NA        NA
+C23   VCCO_16                       NA                 16    NA            NA                  NA        NA
+D30   VCCO_16                       NA                 16    NA            NA                  NA        NA
+E27   VCCO_16                       NA                 16    NA            NA                  NA        NA
+F24   VCCO_16                       NA                 16    NA            NA                  NA        NA
+H28   VCCO_16                       NA                 16    NA            NA                  NA        NA
+A19   VCCO_17                       NA                 17    NA            NA                  NA        NA
+B16   VCCO_17                       NA                 17    NA            NA                  NA        NA
+D20   VCCO_17                       NA                 17    NA            NA                  NA        NA
+E17   VCCO_17                       NA                 17    NA            NA                  NA        NA
+G21   VCCO_17                       NA                 17    NA            NA                  NA        NA
+H18   VCCO_17                       NA                 17    NA            NA                  NA        NA
+L19   VCCO_17                       NA                 17    NA            NA                  NA        NA
+C13   VCCO_18                       NA                 18    NA            NA                  NA        NA
+D10   VCCO_18                       NA                 18    NA            NA                  NA        NA
+F14   VCCO_18                       NA                 18    NA            NA                  NA        NA
+G11   VCCO_18                       NA                 18    NA            NA                  NA        NA
+J15   VCCO_18                       NA                 18    NA            NA                  NA        NA
+K12   VCCO_18                       NA                 18    NA            NA                  NA        NA
+AB6   VCCO_0                        NA                 0     NA            NA                  NA        NA
+T9    VCCO_0                        NA                 0     NA            NA                  NA        NA
+                                                                                                         
+Total Number of Pins Generated, 900                                                                                                   
--- a/hdl/testbench/svec7_test_top/Manifest.py
+++ b/hdl/testbench/svec7_test_top/Manifest.py
+action = "simulation"
+target = "xilinx"
+sim_tool = "modelsim"
+sim_top = "main"
+vcom_opt = "-93 -mixedsvvh"
+
+syn_device = "xc7k325t"
+svec_template_ucf = []
+board = "svec7"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
+include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm", 
+               "../../../../general-cores/sim",
+		"../../../../general-cores/modules/wishbone/wb_spi",
+		"../../../../general-cores/modules/wishbone/wb_lm32/src",
+	       "." ]
+
+files = [ "main.sv", "buildinfo_pkg.vhd" ]
+
+modules = {
+  "local" :  [ "../../rtl/svec7",
+	"../../top/svec7_test",
+      "../../../../wr-cores",
+      "../../../../general-cores",
+      "../../../../vme64x-core"
+      
+  ],
+}
+
+# Do not fail during hdlmake fetch
+try:
+    exec(open("../../../../general-cores/tools/gen_buildinfo.py").read())
+except:
+    pass
--- a/hdl/testbench/svec7_test_top/main.sv
+++ b/hdl/testbench/svec7_test_top/main.sv
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
+
+import wishbone_pkg::*;
+   
+module main;
+   reg rst_n = 0;
+   reg clk_125m_pllref = 0;
+   wire clk_62m5;
+   wire rst_62m5_n;
+
+   initial begin
+      repeat(20) @(posedge clk_125m_pllref);
+      rst_n = 1;
+   end
+   
+   // 125Mhz
+   always #4ns clk_125m_pllref <= ~clk_125m_pllref;
+
+   IVME64X VME(rst_n);
+
+   `DECLARE_VME_BUFFERS(VME.slave);
+
+   logic             ddr_reset_n;
+   logic             ddr_ck_p;
+   logic             ddr_ck_n;
+   logic             ddr_cke;
+   logic             ddr_ras_n;
+   logic             ddr_cas_n;
+   logic             ddr_we_n;
+   wire  [7:0]       ddr_dm;
+   logic [2:0]       ddr_ba;
+   logic [14:0]      ddr_a;
+   wire  [63:0]      ddr_dq;
+   wire  [7:0]       ddr_dqs_p;
+   wire  [7:0]       ddr_dqs_n;
+   wire              ddr_rzq;
+   logic             ddr_odt;
+
+   logic [4:0]       slot_id = 5'h8;
+
+   svec7_test_top
+     #(
+       .g_SIMULATION(1'b1)
+       )
+      DUT (
+	   .rst_n_i(rst_n),
+
+         .clk_62m5_pllref_p_i      (clk_125m_pllref),
+         .clk_62m5_pllref_n_i      (~clk_125m_pllref),
+
+         .clk_20m_vcxo_i (1'b0),
+         .clk_125m_gtx_n_i (1'b0),
+         .clk_125m_gtx_p_i (1'b1),
+
+     
+         .vme_as_n_i               (VME_AS_n),
+         .vme_sysreset_n_i         (VME_RST_n),
+         .vme_write_n_i            (VME_WRITE_n),
+         .vme_am_i                 (VME_AM),
+         .vme_ds_n_i               (VME_DS_n),
+         .vme_gap_i                (^slot_id),
+         .vme_ga_i                 (~slot_id),
+         .vme_berr_o               (VME_BERR),
+         .vme_dtack_n_o            (VME_DTACK_n),
+         .vme_retry_n_o            (VME_RETRY_n),
+         .vme_retry_oe_o           (VME_RETRY_OE),
+         .vme_lword_n_b            (VME_LWORD_n),
+         .vme_addr_b               (VME_ADDR),
+         .vme_data_b               (VME_DATA),
+         .vme_irq_o                (VME_IRQ_n),
+         .vme_iack_n_i             (VME_IACK_n),
+         .vme_iackin_n_i           (VME_IACKIN_n),
+         .vme_iackout_n_o          (VME_IACKOUT_n),
+         .vme_dtack_oe_o           (VME_DTACK_OE),
+         .vme_data_dir_o           (VME_DATA_DIR),
+         .vme_data_oe_n_o          (VME_DATA_OE_N),
+         .vme_addr_dir_o           (VME_ADDR_DIR),
+         .vme_addr_oe_n_o          (VME_ADDR_OE_N),
+	   
+         .fmc0_scl_b (),
+         .fmc0_sda_b (),
+         .fmc1_scl_b (),
+         .fmc1_sda_b (),
+         .fmc0_prsnt_m2c_n_i (),
+         .fmc1_prsnt_m2c_n_i (),
+
+         .onewire_b (),
+
+         .carrier_scl_b (),
+         .carrier_sda_b (),
+
+      //   .spi_sclk_o (),
+         .spi_ncs_o (),
+         .spi_mosi_o (),
+         .spi_miso_i (),
+
+         .uart_rxd_i (),
+         .uart_txd_o (),
+
+         .pll20dac_din_o (),
+         .pll20dac_sclk_o (),
+         .pll20dac_sync_n_o (),
+         .pll25dac_din_o (),
+         .pll25dac_sclk_o (),
+         .pll25dac_sync_n_o (),
+
+         .sfp_txp_o (),
+         .sfp_txn_o (),
+         .sfp_rxp_i (),
+         .sfp_rxn_i (),
+         .sfp_mod_def0_i (),
+         .sfp_mod_def1_b (),
+         .sfp_mod_def2_b (),
+         .sfp_rate_select_o (),
+         .sfp_tx_fault_i (),
+         .sfp_tx_disable_o (),
+         .sfp_los_i (),
+
+         .ddr_a_o                  (ddr_a),
+         .ddr_ba_o                 (ddr_ba),
+         .ddr_cas_n_o              (ddr_cas_n),
+         .ddr_ck_p_o               (ddr_ck_p),
+         .ddr_ck_n_o               (ddr_ck_n),
+         .ddr_cke_o                (ddr_cke),
+         .ddr_dq_b                 (ddr_dq),
+         .ddr_odt_o                (ddr_odt),
+         .ddr_ras_n_o              (ddr_ras_n),
+         .ddr_reset_n_o            (ddr_reset_n),
+         .ddr_rzq_b                (ddr_rzq),
+         .ddr_dm_o                 (ddr_dm),
+         .ddr_dqs_n_b              (ddr_dqs_n),
+         .ddr_dqs_p_b              (ddr_dqs_p),
+         .ddr_we_n_o               (ddr_we_n),
+	 .ddr_cs_n_o               (ddr_cs_n),
+
+    
+         .pcbrev_i (5'h2)
+ 
+     
+  	  );
+
+/* -----\/----- EXCLUDED -----\/-----
+   ddr3
+     cmp_ddr4 (
+      .rst_n   (ddr_reset_n),
+      .ck      (ddr_ck_p),
+      .ck_n    (ddr_ck_n),
+      .cke     (ddr_cke),
+      .cs_n    (1'b0),
+      .ras_n   (ddr_ras_n),
+      .cas_n   (ddr_cas_n),
+      .we_n    (ddr_we_n),
+      .dm_tdqs ({ddr_dm[1], ddr_dm[0]}),
+      .ba      (ddr_ba),
+      .addr    (ddr_a),
+      .dq      (ddr_dq),
+      .dqs     ({ddr_dqs_p[1],ddr_dqs_p[0]}),
+      .dqs_n   ({ddr_dqs_n[1],ddr_dqs_n[0]}),
+      .odt     (ddr_odt),
+      .tdqs_n  ()
+	  );
+ -----/\----- EXCLUDED -----/\----- */
+
+   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
+      uint64_t rv;
+
+      /* map func0 to 0x80000000, A32 */
+
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+
+
+      acc.set_default_modifiers(A32 | D32 | SINGLE);
+   endtask // init_vme64x_core
+     
+   
+   initial begin
+      uint64_t d;
+      
+      int i, result;
+      
+      automatic CBusAccessor_VME64x acc = new(VME.tb);
+//      automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
+
+      #1us;
+      init_vme64x_core(acc);
+
+      //  Display meta data
+      for (i = 0; i < 8'h20; i += 4)
+      begin
+         acc.read('h80000000 | i, d, A32|SINGLE|D32);
+         $display("Read %x: %x", i, d);
+      end
+
+      acc.read('h80000050, d, A32|SINGLE|D32);
+      $display("ddr status: %x", d);
+
+      //  Write ddr4
+  //    ddr4_acc.set_mode(PIPELINED);
+    //  ddr4_acc.write(0, 64'h1122334455667788, 8);
+
+      //  Read DDR4
+      acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
+      $display("Read data: %08x", d);
+      acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
+      $display("Read addr: %x", d);
+
+      acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
+      $display("Read data: %08x", d);
+      acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
+      $display("Read addr: %x", d);
+
+/*
+       acc.write('h80010000, d, A24|SINGLE|D32);
+      acc.read('h80010000, d, A24|SINGLE|D32);
+
+      acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
+      acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
+
+      acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
+      acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
+      
+      $display("Read1: %x\n", d);
+  */    
+   end
+
+  
+endmodule // main
+
+
+
--- a/hdl/testbench/svec7_test_top/run.do
+++ b/hdl/testbench/svec7_test_top/run.do
+vsim -quiet -t 10fs -L unisim work.main -novopt
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+radix -hexadecimal
+
+log -r /*
+
+run 1us
+
+wave zoomfull
--- a/hdl/testbench/svec7_test_top/wave.do
+++ b/hdl/testbench/svec7_test_top/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/rst_n_i
+add wave -noupdate /main/DUT/clk_20m_vcxo_i
+add wave -noupdate /main/DUT/clk_62m5_pllref_p_i
+add wave -noupdate /main/DUT/clk_62m5_pllref_n_i
+add wave -noupdate /main/DUT/clk_125m_gtx_n_i
+add wave -noupdate /main/DUT/clk_125m_gtx_p_i
+add wave -noupdate /main/DUT/clk_fpga2_p_i
+add wave -noupdate /main/DUT/clk_fpga2_n_i
+add wave -noupdate /main/DUT/clk_si57x_p_i
+add wave -noupdate /main/DUT/clk_si57x_n_i
+add wave -noupdate /main/DUT/vme_write_n_i
+add wave -noupdate /main/DUT/vme_sysreset_n_i
+add wave -noupdate /main/DUT/vme_retry_oe_o
+add wave -noupdate /main/DUT/vme_retry_n_o
+add wave -noupdate /main/DUT/vme_lword_n_b
+add wave -noupdate /main/DUT/vme_iackout_n_o
+add wave -noupdate /main/DUT/vme_iackin_n_i
+add wave -noupdate /main/DUT/vme_iack_n_i
+add wave -noupdate /main/DUT/vme_gap_i
+add wave -noupdate /main/DUT/vme_dtack_oe_o
+add wave -noupdate /main/DUT/vme_dtack_n_o
+add wave -noupdate /main/DUT/vme_ds_n_i
+add wave -noupdate /main/DUT/vme_data_oe_n_o
+add wave -noupdate /main/DUT/vme_data_dir_o
+add wave -noupdate /main/DUT/vme_berr_o
+add wave -noupdate /main/DUT/vme_as_n_i
+add wave -noupdate /main/DUT/vme_addr_oe_n_o
+add wave -noupdate /main/DUT/vme_addr_dir_o
+add wave -noupdate /main/DUT/vme_irq_o
+add wave -noupdate /main/DUT/vme_ga_i
+add wave -noupdate /main/DUT/vme_data_b
+add wave -noupdate /main/DUT/vme_am_i
+add wave -noupdate /main/DUT/vme_addr_b
+add wave -noupdate /main/DUT/vme_noga_i
+add wave -noupdate /main/DUT/vme_use_ga_i
+add wave -noupdate /main/DUT/pll20dac_din_o
+add wave -noupdate /main/DUT/pll20dac_sclk_o
+add wave -noupdate /main/DUT/pll20dac_sync_n_o
+add wave -noupdate /main/DUT/pll25dac_din_o
+add wave -noupdate /main/DUT/pll25dac_sclk_o
+add wave -noupdate /main/DUT/pll25dac_sync_n_o
+add wave -noupdate /main/DUT/sfp_txp_o
+add wave -noupdate /main/DUT/sfp_txn_o
+add wave -noupdate /main/DUT/sfp_rxp_i
+add wave -noupdate /main/DUT/sfp_rxn_i
+add wave -noupdate /main/DUT/sfp_mod_def0_i
+add wave -noupdate /main/DUT/sfp_mod_def1_b
+add wave -noupdate /main/DUT/sfp_mod_def2_b
+add wave -noupdate /main/DUT/sfp_rate_select_o
+add wave -noupdate /main/DUT/sfp_tx_fault_i
+add wave -noupdate /main/DUT/sfp_tx_disable_o
+add wave -noupdate /main/DUT/sfp_los_i
+add wave -noupdate /main/DUT/carrier_scl_b
+add wave -noupdate /main/DUT/carrier_sda_b
+add wave -noupdate /main/DUT/pcbrev_i
+add wave -noupdate /main/DUT/onewire_b
+add wave -noupdate /main/DUT/uart_rxd_i
+add wave -noupdate /main/DUT/uart_txd_o
+add wave -noupdate /main/DUT/spi_ncs_o
+add wave -noupdate /main/DUT/spi_mosi_o
+add wave -noupdate /main/DUT/spi_miso_i
+add wave -noupdate /main/DUT/fp_led_line_oen_o
+add wave -noupdate /main/DUT/fp_led_line_o
+add wave -noupdate /main/DUT/fp_led_column_o
+add wave -noupdate /main/DUT/fp_gpio1_b
+add wave -noupdate /main/DUT/fp_gpio2_b
+add wave -noupdate /main/DUT/fp_gpio3_b
+add wave -noupdate /main/DUT/fp_gpio4_b
+add wave -noupdate /main/DUT/fp_term_en_o
+add wave -noupdate /main/DUT/fp_gpio1_a2b_o
+add wave -noupdate /main/DUT/fp_gpio2_a2b_o
+add wave -noupdate /main/DUT/fp_gpio34_a2b_o
+add wave -noupdate /main/DUT/fp_pushbutton_n_i
+add wave -noupdate /main/DUT/fmc0_la_p_b
+add wave -noupdate /main/DUT/fmc0_la_n_b
+add wave -noupdate /main/DUT/fmc0_pg_i
+add wave -noupdate /main/DUT/fmc0_prsnt_m2c_n_i
+add wave -noupdate /main/DUT/fmc0_clk_m2c_p_i
+add wave -noupdate /main/DUT/fmc0_clk_m2c_n_i
+add wave -noupdate /main/DUT/fmc0_scl_b
+add wave -noupdate /main/DUT/fmc0_sda_b
+add wave -noupdate /main/DUT/fmc0_tck_o
+add wave -noupdate /main/DUT/fmc0_tms_o
+add wave -noupdate /main/DUT/fmc0_tdi_o
+add wave -noupdate /main/DUT/fmc0_tdo_i
+add wave -noupdate /main/DUT/fmc1_la_p_b
+add wave -noupdate /main/DUT/fmc1_la_n_b
+add wave -noupdate /main/DUT/fmc1_pg_i
+add wave -noupdate /main/DUT/fmc1_prsnt_m2c_n_i
+add wave -noupdate /main/DUT/fmc1_clk_m2c_p_i
+add wave -noupdate /main/DUT/fmc1_clk_m2c_n_i
+add wave -noupdate /main/DUT/fmc1_scl_b
+add wave -noupdate /main/DUT/fmc1_sda_b
+add wave -noupdate /main/DUT/fmc1_tck_o
+add wave -noupdate /main/DUT/fmc1_tms_o
+add wave -noupdate /main/DUT/fmc1_tdi_o
+add wave -noupdate /main/DUT/fmc1_tdo_i
+add wave -noupdate /main/DUT/p2_p_b
+add wave -noupdate /main/DUT/p2_n_b
+add wave -noupdate /main/DUT/ddr_a_o
+add wave -noupdate /main/DUT/ddr_ba_o
+add wave -noupdate /main/DUT/ddr_cas_n_o
+add wave -noupdate /main/DUT/ddr_ck_n_o
+add wave -noupdate /main/DUT/ddr_ck_p_o
+add wave -noupdate /main/DUT/ddr_cke_o
+add wave -noupdate /main/DUT/ddr_dq_b
+add wave -noupdate /main/DUT/ddr_ldm_o
+add wave -noupdate /main/DUT/ddr_dqs_n_b
+add wave -noupdate /main/DUT/ddr_dqs_p_b
+add wave -noupdate /main/DUT/ddr_odt_o
+add wave -noupdate /main/DUT/ddr_ras_n_o
+add wave -noupdate /main/DUT/ddr_reset_n_o
+add wave -noupdate /main/DUT/ddr_rzq_b
+add wave -noupdate /main/DUT/ddr_dm_o
+add wave -noupdate /main/DUT/ddr_we_n_o
+add wave -noupdate /main/DUT/ddr_cs_n_o
+add wave -noupdate /main/DUT/si57x_scl_b
+add wave -noupdate /main/DUT/si57x_sda_b
+add wave -noupdate /main/DUT/si57x_oe_o
+add wave -noupdate /main/DUT/si57x_tune_o
+add wave -noupdate /main/DUT/cnx_master_out
+add wave -noupdate /main/DUT/cnx_master_in
+add wave -noupdate /main/DUT/cnx_slave_out
+add wave -noupdate /main/DUT/cnx_slave_in
+add wave -noupdate /main/DUT/areset_n
+add wave -noupdate /main/DUT/clk_sys_62m5
+add wave -noupdate /main/DUT/rst_sys_62m5_n
+add wave -noupdate /main/DUT/clk_ref_62m5
+add wave -noupdate /main/DUT/clk_ext_ref
+add wave -noupdate /main/DUT/eeprom_sda_in
+add wave -noupdate /main/DUT/eeprom_sda_out
+add wave -noupdate /main/DUT/eeprom_scl_in
+add wave -noupdate /main/DUT/eeprom_scl_out
+add wave -noupdate /main/DUT/vme_data_b_out
+add wave -noupdate /main/DUT/vme_addr_b_out
+add wave -noupdate /main/DUT/vme_lword_n_b_out
+add wave -noupdate /main/DUT/vme_data_dir_int
+add wave -noupdate /main/DUT/vme_addr_dir_int
+add wave -noupdate /main/DUT/vme_ga
+add wave -noupdate /main/DUT/vme_berr_n
+add wave -noupdate /main/DUT/vme_irq_n
+add wave -noupdate /main/DUT/vme_access_led
+add wave -noupdate /main/DUT/sfp_sda_in
+add wave -noupdate /main/DUT/sfp_sda_out
+add wave -noupdate /main/DUT/sfp_scl_in
+add wave -noupdate /main/DUT/sfp_scl_out
+add wave -noupdate /main/DUT/pps
+add wave -noupdate /main/DUT/pps_led
+add wave -noupdate /main/DUT/pps_ext_in
+add wave -noupdate /main/DUT/svec_led
+add wave -noupdate /main/DUT/wr_led_link
+add wave -noupdate /main/DUT/wr_led_act
+add wave -noupdate /main/DUT/irq_vector
+add wave -noupdate /main/DUT/ddr_axi4_out
+add wave -noupdate /main/DUT/ddr_axi4_in
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {73840400 fs} 0}
+configure wave -namecolwidth 252
+configure wave -valuecolwidth 364
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits fs
+update
+WaveRestoreZoom {0 fs} {858329180 fs}
--- a/hdl/top/svec7_test/Manifest.py
+++ b/hdl/top/svec7_test/Manifest.py
+files = [
+    "svec7_test_top.vhd",
+]
+
--- a/hdl/top/svec7_test/svec7_test_top.vhd
+++ b/hdl/top/svec7_test/svec7_test_top.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+--------------------------------------------------------------------------------
+--
+-- unit name:   wrtd_ref_svec_tdc_fd
+--
+-- description: Top entity for WRTD reference design
+--
+-- Top level design of the SVEC-based WRTD node, with
+-- an FMC TDC in slot 1 and an FMC Fine Delay in slot 2.
+--
+-- This is the standard pulse-in/pulse-out WRTD node, with the FMC TDC
+-- injecting pulses into the WR network in the form of WRTD messages and
+-- the FMC Fine Delay converting those messages back to pulses at the
+-- destination.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2014-2019
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.gencores_pkg.all;
+use work.wishbone_pkg.all;
+use work.wr_board_pkg.all;
+use work.wr_fabric_pkg.all;
+use work.axi4_pkg.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+entity svec7_test_top is
+  generic (
+    g_WRPC_INITF : string  := "../../../../wr-cores/bin/wrpc/wrc_phy16.bram";
+    -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
+    -- changed to non-zero in the instantiation of the top level DUT in the
+    -- testbench. Its purpose is to reduce some internal counters/timeouts
+    -- to speed up simulations.
+    g_SIMULATION : integer := 0);
+  port (
+    ---------------------------------------------------------------------------
+    -- Clocks/resets
+    ---------------------------------------------------------------------------
+
+    -- Reset from system fpga
+    rst_n_i : in std_logic;
+
+    -- Local oscillators
+    clk_20m_vcxo_i : in std_logic;      -- 20MHz VCXO clock
+
+    clk_62m5_pllref_p_i : in std_logic;  -- 62.5 MHz PLL reference
+    clk_62m5_pllref_n_i : in std_logic;
+
+    clk_125m_gtx_n_i : in std_logic;    -- 125 MHz GTX reference
+    clk_125m_gtx_p_i : in std_logic;
+
+    -- PLL_2AFPGA pins
+    clk_fpga2_p_i : in std_logic;
+    clk_fpga2_n_i : in std_logic;
+
+    clk_si57x_p_i : in std_logic;
+    clk_si57x_n_i : in std_logic;
+
+
+    ---------------------------------------------------------------------------
+    -- VME interface
+    ---------------------------------------------------------------------------
+
+    vme_write_n_i    : in    std_logic;
+    vme_sysreset_n_i : in    std_logic;
+    vme_retry_oe_o   : out   std_logic;
+    vme_retry_n_o    : out   std_logic;
+    vme_lword_n_b    : inout std_logic;
+    vme_iackout_n_o  : out   std_logic;
+    vme_iackin_n_i   : in    std_logic;
+    vme_iack_n_i     : in    std_logic;
+    vme_gap_i        : in    std_logic;
+    vme_dtack_oe_o   : out   std_logic;
+    vme_dtack_n_o    : out   std_logic;
+    vme_ds_n_i       : in    std_logic_vector(1 downto 0);
+    vme_data_oe_n_o  : out   std_logic;
+    vme_data_dir_o   : out   std_logic;
+    vme_berr_o       : out   std_logic;
+    vme_as_n_i       : in    std_logic;
+    vme_addr_oe_n_o  : out   std_logic;
+    vme_addr_dir_o   : out   std_logic;
+    vme_irq_o        : out   std_logic_vector(7 downto 1);
+    vme_ga_i         : in    std_logic_vector(4 downto 0);
+    vme_data_b       : inout std_logic_vector(31 downto 0);
+    vme_am_i         : in    std_logic_vector(5 downto 0);
+    vme_addr_b       : inout std_logic_vector(31 downto 1);
+
+
+    vme_noga_i   : in std_logic_vector(4 downto 0);
+    vme_use_ga_i : in std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SPI interfaces to DACs
+    ---------------------------------------------------------------------------
+
+    pll20dac_din_o    : out std_logic;
+    pll20dac_sclk_o   : out std_logic;
+    pll20dac_sync_n_o : out std_logic;
+    pll25dac_din_o    : out std_logic;
+    pll25dac_sclk_o   : out std_logic;
+    pll25dac_sync_n_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SFP I/O for transceiver
+    ---------------------------------------------------------------------------
+
+    sfp_txp_o         : out   std_logic;
+    sfp_txn_o         : out   std_logic;
+    sfp_rxp_i         : in    std_logic;
+    sfp_rxn_i         : in    std_logic;
+    sfp_mod_def0_i    : in    std_logic;  -- sfp detect
+    sfp_mod_def1_b    : inout std_logic;  -- scl
+    sfp_mod_def2_b    : inout std_logic;  -- sda
+    sfp_rate_select_o : out   std_logic;
+    sfp_tx_fault_i    : in    std_logic;
+    sfp_tx_disable_o  : out   std_logic;
+    sfp_los_i         : in    std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Carrier I2C EEPROM
+    ---------------------------------------------------------------------------
+
+    carrier_scl_b : inout std_logic;
+    carrier_sda_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- PCB version
+    ---------------------------------------------------------------------------
+    pcbrev_i : in std_logic_vector(4 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- Onewire interface
+    ---------------------------------------------------------------------------
+
+    onewire_b : inout std_logic;
+
+    ---------------------------------------------------------------------------
+    -- UART
+    ---------------------------------------------------------------------------
+
+    uart_rxd_i : in  std_logic;
+    uart_txd_o : out std_logic;
+
+    ---------------------------------------------------------------------------
+    -- SPI (flash is connected to SFPGA and routed to AFPGA
+    -- once the boot process is complete)
+    ---------------------------------------------------------------------------
+
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- Carrier front panel LEDs and IOs
+    ---------------------------------------------------------------------------
+
+    fp_led_line_oen_o : out std_logic_vector(1 downto 0);
+    fp_led_line_o     : out std_logic_vector(1 downto 0);
+    fp_led_column_o   : out std_logic_vector(3 downto 0);
+
+    fp_gpio1_b      : out std_logic;    -- PPS output
+    fp_gpio2_b      : out std_logic;    -- not used
+    fp_gpio3_b      : in  std_logic;    -- ext 10MHz clock input
+    fp_gpio4_b      : in  std_logic;    -- ext PPS input
+    fp_term_en_o    : out std_logic_vector(4 downto 1);
+    fp_gpio1_a2b_o  : out std_logic;
+    fp_gpio2_a2b_o  : out std_logic;
+    fp_gpio34_a2b_o : out std_logic;
+
+    fp_pushbutton_n_i : in std_logic;
+
+
+    ---------------------------------------------------------------------------
+    -- FMC slot 1 pins
+    ---------------------------------------------------------------------------
+
+    fmc0_la_p_b : inout std_logic_vector(33 downto 0);
+    fmc0_la_n_b : inout std_logic_vector(33 downto 0);
+
+    fmc0_pg_i          : in std_logic;
+    fmc0_prsnt_m2c_n_i : in std_logic;
+    fmc0_clk_m2c_p_i   : in std_logic_vector(1 downto 0);
+    fmc0_clk_m2c_n_i   : in std_logic_vector(1 downto 0);
+
+    fmc0_scl_b : inout std_logic;
+    fmc0_sda_b : inout std_logic;
+
+    fmc0_tck_o : out std_logic;
+    fmc0_tms_o : out std_logic;
+    fmc0_tdi_o : out std_logic;
+    fmc0_tdo_i : in  std_logic;
+
+    ---------------------------------------------------------------------------
+    -- FMC slot 2 pins 
+    ---------------------------------------------------------------------------
+
+    fmc1_la_p_b : inout std_logic_vector(33 downto 0);
+    fmc1_la_n_b : inout std_logic_vector(33 downto 0);
+
+    fmc1_pg_i          : in std_logic;
+    fmc1_prsnt_m2c_n_i : in std_logic;
+    fmc1_clk_m2c_p_i   : in std_logic_vector(1 downto 0);
+    fmc1_clk_m2c_n_i   : in std_logic_vector(1 downto 0);
+
+    fmc1_scl_b : inout std_logic;
+    fmc1_sda_b : inout std_logic;
+
+    fmc1_tck_o : out std_logic;
+    fmc1_tms_o : out std_logic;
+    fmc1_tdi_o : out std_logic;
+    fmc1_tdo_i : in  std_logic;
+
+
+    -- P2 pins
+
+    p2_p_b : inout std_logic_vector(19 downto 0);
+    p2_n_b : inout std_logic_vector(19 downto 0);
+
+    ---------------------------------------------------------------------------
+    -- DDR Controller
+    ---------------------------------------------------------------------------
+
+    ddr_a_o       : out   std_logic_vector(14 downto 0);
+    ddr_ba_o      : out   std_logic_vector(2 downto 0);
+    ddr_cas_n_o   : out   std_logic;
+    ddr_ck_n_o    : out   std_logic;
+    ddr_ck_p_o    : out   std_logic;
+    ddr_cke_o     : out   std_logic;
+    ddr_dq_b      : inout std_logic_vector(63 downto 0);
+    ddr_ldm_o     : out   std_logic;
+    ddr_dqs_n_b   : inout std_logic_vector(7 downto 0);
+    ddr_dqs_p_b   : inout std_logic_vector(7 downto 0);
+    ddr_odt_o     : out   std_logic;
+    ddr_ras_n_o   : out   std_logic;
+    ddr_reset_n_o : out   std_logic;
+    ddr_rzq_b     : inout std_logic;
+    ddr_dm_o      : out   std_logic_vector(7 downto 0);
+    ddr_we_n_o    : out   std_logic;
+    ddr_cs_n_o    : out   std_logic;
+
+    si57x_scl_b : inout std_logic;
+    si57x_sda_b : inout std_logic;
+
+    si57x_oe_o   : out std_logic;
+    si57x_tune_o : out std_logic
+
+    );
+
+end entity svec7_test_top;
+
+architecture arch of svec7_test_top is
+
+  -----------------------------------------------------------------------------
+  -- Constants
+  -----------------------------------------------------------------------------
+
+  -- WRTD Node identification (WTN2)
+  constant c_WRTD_NODE_ID : std_logic_vector(31 downto 0) := x"5754_4E02";
+
+  -- Number of masters attached to the primary wishbone crossbar
+  constant c_NUM_WB_MASTERS : integer := 1;
+
+  -- Number of slaves attached to the primary wishbone crossbar
+  constant c_NUM_WB_SLAVES : integer := 3;
+
+  -- Primary Wishbone master(s) offsets
+  constant c_WB_MASTER_VME : integer := 0;
+
+  -- Primary Wishbone slave(s) offsets
+  constant c_WB_SLAVE_METADATA  : integer := 0;
+  constant c_WB_SLAVE_GPIO      : integer := 1;
+  constant c_WB_SLAVE_CLOCK_MON : integer := 2;
+
+  -- Convention metadata base address
+  constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
+
+  -- Primary wishbone crossbar layout
+  constant c_WB_LAYOUT_ADDR :
+    t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+      c_WB_SLAVE_METADATA  => c_METADATA_ADDR,
+      c_WB_SLAVE_GPIO      => x"0000_8000",
+      c_WB_SLAVE_CLOCK_MON => x"0001_0000");
+
+  constant c_WB_LAYOUT_MASK :
+    t_wishbone_address_array(c_NUM_WB_SLAVES - 1 downto 0) := (
+      c_WB_SLAVE_METADATA  => x"0003_ffc0",   --    0x40 bytes
+      c_WB_SLAVE_GPIO      => x"0003_f800",
+      c_WB_SLAVE_CLOCK_MON => x"0003_f800");  -- 0x20000 bytes
+
+
+
+  -----------------------------------------------------------------------------
+  -- Signals
+  -----------------------------------------------------------------------------
+
+  -- Wishbone buse(s) from masters attached to crossbar
+  signal cnx_master_out : t_wishbone_master_out_array(c_NUM_WB_MASTERS-1 downto 0);
+  signal cnx_master_in  : t_wishbone_master_in_array(c_NUM_WB_MASTERS-1 downto 0);
+
+  -- Wishbone buse(s) to slaves attached to crossbar
+  signal cnx_slave_out : t_wishbone_slave_out_array(c_NUM_WB_SLAVES-1 downto 0);
+  signal cnx_slave_in  : t_wishbone_slave_in_array(c_NUM_WB_SLAVES-1 downto 0);
+
+  -- clock and reset
+  signal areset_n       : std_logic;
+  signal clk_sys_62m5   : std_logic;
+  signal rst_sys_62m5_n : std_logic;
+  signal clk_ref_62m5   : std_logic;
+  signal clk_ext_ref    : std_logic;
+
+  attribute keep : string;
+
+  -- I2C EEPROM
+  signal eeprom_sda_in  : std_logic;
+  signal eeprom_sda_out : std_logic;
+  signal eeprom_scl_in  : std_logic;
+  signal eeprom_scl_out : std_logic;
+
+  -- VME
+  signal vme_data_b_out    : std_logic_vector(31 downto 0);
+  signal vme_addr_b_out    : std_logic_vector(31 downto 1);
+  signal vme_lword_n_b_out : std_logic;
+  signal vme_data_dir_int  : std_logic;
+  signal vme_addr_dir_int  : std_logic;
+  signal vme_ga            : std_logic_vector(5 downto 0);
+  signal vme_berr_n        : std_logic;
+  signal vme_irq_n         : std_logic_vector(7 downto 1);
+  signal vme_access_led    : std_logic;
+
+  -- SFP
+  signal sfp_sda_in  : std_logic;
+  signal sfp_sda_out : std_logic;
+  signal sfp_scl_in  : std_logic;
+  signal sfp_scl_out : std_logic;
+
+  -- LEDs and GPIO
+  signal pps         : std_logic;
+  signal pps_led     : std_logic;
+  signal pps_ext_in  : std_logic;
+  signal svec_led    : std_logic_vector(15 downto 0);
+  signal wr_led_link : std_logic;
+  signal wr_led_act  : std_logic;
+
+  -- Interrupts
+  signal irq_vector : std_logic_vector(5 downto 0);
+
+  --  MT endpoints
+
+  attribute iob        : string;
+  attribute iob of pps : signal is "FORCE";
+
+  signal ddr_axi4_out : t_axi4_full_master_in_512;
+  signal ddr_axi4_in  : t_axi4_full_master_out_512;
+
+  signal gpio_out : std_logic_vector(255 downto 0);
+  signal gpio_in  : std_logic_vector(255 downto 0);
+  signal gpio_oen : std_logic_vector(255 downto 0);
+
+
+  signal clk_fpga2 : std_logic;
+  signal clk_si57x : std_logic;
+
+  signal fmc0_clk : std_logic_vector(1 downto 0);
+  signal fmc1_clk : std_logic_vector(1 downto 0);
+
+
+begin  -- architecture arch
+
+  areset_n <= vme_sysreset_n_i and rst_n_i;
+
+  cmp_buf1 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => clk_fpga2,                  -- Buffer output
+      I  => clk_fpga2_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+      IB => clk_fpga2_n_i  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  cmp_buf2 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => clk_si57x,                  -- Buffer output
+      I  => clk_si57x_p_i,  -- Diff_p buffer input (connect directly to top-level port)
+      IB => clk_si57x_n_i  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  cmp_buf6 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => fmc0_clk(0),                -- Buffer output
+      I  => fmc0_clk_m2c_p_i(0),  -- Diff_p buffer input (connect directly to top-level port)
+      IB => fmc0_clk_m2c_n_i(0)  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+  cmp_buf3 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => fmc0_clk(1),                -- Buffer output
+      I  => fmc0_clk_m2c_p_i(1),  -- Diff_p buffer input (connect directly to top-level port)
+      IB => fmc0_clk_m2c_n_i(1)  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+
+  cmp_buf4 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => fmc1_clk(0),                -- Buffer output
+      I  => fmc1_clk_m2c_p_i(0),  -- Diff_p buffer input (connect directly to top-level port)
+      IB => fmc1_clk_m2c_n_i(0)  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+
+  cmp_buf5 : IBUFGDS
+    generic map (
+      DIFF_TERM    => true,             -- Differential Termination
+      IBUF_LOW_PWR => true,  -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
+      IOSTANDARD   => "DEFAULT")
+    port map (
+      O  => fmc1_clk(1),                -- Buffer output
+      I  => fmc1_clk_m2c_p_i(1),  -- Diff_p buffer input (connect directly to top-level port)
+      IB => fmc1_clk_m2c_n_i(1)  -- Diff_n buffer input (connect directly to top-level port)
+      );
+
+
+  cmp_xwb_metadata : entity work.xwb_metadata
+    generic map (
+      g_VENDOR_ID    => x"0000_10DC",
+      g_DEVICE_ID    => c_WRTD_NODE_ID,
+      g_VERSION      => x"0100_0000",
+      g_CAPABILITIES => x"0000_0000",
+      g_COMMIT_ID    => (others => '0'))
+    port map (
+      clk_i   => clk_sys_62m5,
+      rst_n_i => rst_sys_62m5_n,
+      wb_i    => cnx_slave_in(c_WB_SLAVE_METADATA),
+      wb_o    => cnx_slave_out(c_WB_SLAVE_METADATA));
+
+  inst_svec_base : entity work.svec7_base_wr
+    generic map (
+      g_WITH_VIC     => true,
+      g_WITH_ONEWIRE => false,
+      g_WITH_SPI     => true,
+      g_WITH_WR      => true,
+      g_WITH_DDR     => true,
+      g_APP_OFFSET   => c_METADATA_ADDR,
+      g_NUM_USER_IRQ => 6,
+      g_DPRAM_INITF  => g_WRPC_INITF,
+      g_AUX_CLKS     => 2,
+      g_FABRIC_IFACE => plain,
+      g_SIMULATION   => g_SIMULATION,
+      g_VERBOSE      => false)
+    port map (
+      rst_n_i             => areset_n,
+      clk_62m5_pllref_p_i => clk_62m5_pllref_p_i,
+      clk_62m5_pllref_n_i => clk_62m5_pllref_n_i,
+      clk_20m_vcxo_i      => clk_20m_vcxo_i,
+      clk_125m_gtx_n_i    => clk_125m_gtx_n_i,
+      clk_125m_gtx_p_i    => clk_125m_gtx_p_i,
+      clk_10m_ext_i       => clk_ext_ref,
+      pps_ext_i           => pps_ext_in,
+      vme_write_n_i       => vme_write_n_i,
+      vme_sysreset_n_i    => vme_sysreset_n_i,
+      vme_retry_oe_o      => vme_retry_oe_o,
+      vme_retry_n_o       => vme_retry_n_o,
+      vme_lword_n_b       => vme_lword_n_b,
+      vme_iackout_n_o     => vme_iackout_n_o,
+      vme_iackin_n_i      => vme_iackin_n_i,
+      vme_iack_n_i        => vme_iack_n_i,
+      vme_gap_i           => vme_gap_i,
+      vme_dtack_oe_o      => vme_dtack_oe_o,
+      vme_dtack_n_o       => vme_dtack_n_o,
+      vme_ds_n_i          => vme_ds_n_i,
+      vme_data_oe_n_o     => vme_data_oe_n_o,
+      vme_data_dir_o      => vme_data_dir_o,
+      vme_berr_o          => vme_berr_o,
+      vme_as_n_i          => vme_as_n_i,
+      vme_addr_oe_n_o     => vme_addr_oe_n_o,
+      vme_addr_dir_o      => vme_addr_dir_o,
+      vme_irq_o           => vme_irq_o,
+      vme_ga_i            => vme_ga_i,
+      vme_data_b          => vme_data_b,
+      vme_am_i            => vme_am_i,
+      vme_addr_b          => vme_addr_b,
+      fmc0_scl_b          => fmc0_scl_b,
+      fmc0_sda_b          => fmc0_sda_b,
+      fmc1_scl_b          => fmc1_scl_b,
+      fmc1_sda_b          => fmc1_sda_b,
+      fmc0_prsnt_m2c_n_i  => fmc0_prsnt_m2c_n_i,
+      fmc1_prsnt_m2c_n_i  => fmc1_prsnt_m2c_n_i,
+      onewire_b           => onewire_b,
+      carrier_scl_b       => carrier_scl_b,
+      carrier_sda_b       => carrier_sda_b,
+      spi_ncs_o           => spi_ncs_o,
+      spi_mosi_o          => spi_mosi_o,
+      spi_miso_i          => spi_miso_i,
+      uart_rxd_i          => uart_rxd_i,
+      uart_txd_o          => uart_txd_o,
+      plldac_sclk_o       => pll20dac_sclk_o,
+      plldac_din_o        => pll20dac_din_o,
+      pll20dac_din_o      => pll20dac_din_o,
+      pll20dac_sclk_o     => pll20dac_sclk_o,
+      pll20dac_sync_n_o   => pll20dac_sync_n_o,
+      pll25dac_din_o      => pll25dac_din_o,
+      pll25dac_sclk_o     => pll25dac_sclk_o,
+      pll25dac_sync_n_o   => pll25dac_sync_n_o,
+      sfp_txp_o           => sfp_txp_o,
+      sfp_txn_o           => sfp_txn_o,
+      sfp_rxp_i           => sfp_rxp_i,
+      sfp_rxn_i           => sfp_rxn_i,
+      sfp_mod_def0_i      => sfp_mod_def0_i,
+      sfp_mod_def1_b      => sfp_mod_def1_b,
+      sfp_mod_def2_b      => sfp_mod_def2_b,
+      sfp_rate_select_o   => sfp_rate_select_o,
+      sfp_tx_fault_i      => sfp_tx_fault_i,
+      sfp_tx_disable_o    => sfp_tx_disable_o,
+      sfp_los_i           => sfp_los_i,
+      pcbrev_i            => pcbrev_i,
+      clk_sys_62m5_o      => clk_sys_62m5,
+      rst_sys_62m5_n_o    => rst_sys_62m5_n,
+      clk_ref_62m5_o      => clk_ref_62m5,
+      rst_ref_62m5_n_o    => open,
+      irq_user_i          => irq_vector,
+      pps_p_o             => pps,
+      pps_led_o           => pps_led,
+      link_ok_o           => open,
+      led_link_o          => wr_led_link,
+      led_act_o           => wr_led_act,
+      app_wb_o            => cnx_master_out(c_WB_MASTER_VME),
+      app_wb_i            => cnx_master_in(c_WB_MASTER_VME),
+      ddr_clk_i           => clk_sys_62m5,
+      ddr_axi4_i          => ddr_axi4_in,
+      ddr_axi4_o          => ddr_axi4_out
+      );
+
+  -----------------------------------------------------------------------------
+  -- Primary wishbone Crossbar
+  -----------------------------------------------------------------------------
+
+  cmp_sdb_crossbar : xwb_crossbar
+    generic map (
+      g_VERBOSE     => false,
+      g_NUM_MASTERS => c_NUM_WB_MASTERS,
+      g_NUM_SLAVES  => c_NUM_WB_SLAVES,
+      g_REGISTERED  => true,
+      g_ADDRESS     => c_WB_LAYOUT_ADDR,
+      g_MASK        => c_WB_LAYOUT_MASK)
+    port map (
+      clk_sys_i => clk_sys_62m5,
+      rst_n_i   => rst_sys_62m5_n,
+      slave_i   => cnx_master_out,
+      slave_o   => cnx_master_in,
+      master_i  => cnx_slave_out,
+      master_o  => cnx_slave_in);
+
+  cmp_vme_led_extend : gc_extend_pulse
+    generic map (
+      g_width => 5000000)
+    port map (
+      clk_i      => clk_sys_62m5,
+      rst_n_i    => rst_sys_62m5_n,
+      pulse_i    => cnx_slave_in(c_WB_MASTER_VME).cyc,
+      extended_o => vme_access_led);
+
+
+  U_GPIO : xwb_gpio_port
+    generic map (
+      g_interface_mode         => PIPELINED,
+      g_address_granularity    => BYTE,
+      g_num_pins               => 256,
+      g_with_builtin_tristates => false)
+    port map (
+      clk_sys_i  => clk_sys_62m5,
+      rst_n_i    => rst_sys_62m5_n,
+      slave_i    => cnx_slave_in(c_WB_SLAVE_GPIO),
+      slave_o    => cnx_slave_out(c_WB_SLAVE_GPIO),
+      gpio_out_o => gpio_out,
+      gpio_in_i  => gpio_in,
+      gpio_oen_o => gpio_oen);
+
+  -----------------------------------------------------------------------------
+  -- Carrier front panel LEDs and LEMOs
+  -----------------------------------------------------------------------------
+
+  cmp_led_controller : gc_bicolor_led_ctrl
+    generic map(
+      g_NB_COLUMN    => 4,
+      g_NB_LINE      => 2,
+      g_CLK_FREQ     => 62500000,       -- in Hz
+      g_REFRESH_RATE => 250             -- in Hz
+      )
+    port map(
+      rst_n_i => rst_sys_62m5_n,
+      clk_i   => clk_sys_62m5,
+
+      led_intensity_i => "1100100",     -- in %
+
+      led_state_i => svec_led,
+
+      column_o   => fp_led_column_o,
+      line_o     => fp_led_line_o,
+      line_oen_o => fp_led_line_oen_o);
+
+  -- LED 4
+  svec_led(1 downto 0)   <= c_LED_GREEN     when wr_led_link = '1'    else c_LED_RED;
+  -- LED 3
+  svec_led(3 downto 2)   <= c_LED_OFF;  --     when tm_clk_aux_locked(1) = '1' else c_LED_RED;
+  -- LED 2
+  svec_led(5 downto 4)   <= c_LED_OFF;  --    when tm_time_valid = '1'        else c_LED_RED;
+  -- LED 1
+  svec_led(7 downto 6)   <= c_LED_RED_GREEN when vme_access_led = '1' else c_LED_OFF;
+  -- LED 8
+  svec_led(9 downto 8)   <= c_LED_RED_GREEN when wr_led_act = '1'     else c_LED_OFF;
+  -- LED 7
+  svec_led(11 downto 10) <= c_LED_OFF;  --     when tm_clk_aux_locked(0) = '1' else c_LED_RED;
+  -- LED 6
+  svec_led(13 downto 12) <= c_LED_OFF;
+  -- LED 5
+  svec_led(15 downto 14) <= c_LED_GREEN     when pps_led = '1'        else c_LED_OFF;
+
+  -- Front panel IO configuration
+  fp_gpio1_b      <= pps;
+  fp_gpio2_b      <= gpio_out(0);
+  clk_ext_ref     <= fp_gpio3_b;
+  pps_ext_in      <= fp_gpio4_b;
+  fp_term_en_o    <= (others => '0');
+  fp_gpio1_a2b_o  <= gpio_out(1);
+  fp_gpio2_a2b_o  <= gpio_out(2);
+  fp_gpio34_a2b_o <= gpio_out(3);
+
+
+  gpio_in(4 downto 0) <= vme_noga_i;
+  gpio_in(5)          <= vme_use_ga_i;
+
+
+  gen_fmc_iobufs : for i in 0 to 33 generate
+    cmp_buf_fmc0 : IOBUFDS
+      generic map (
+        DIFF_TERM    => true,
+        IBUF_LOW_PWR => true,
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O   => gpio_in(6 + i),
+        IO  => fmc0_la_p_b(i),
+        IOB => fmc0_la_n_b(i),
+        I   => gpio_out(6+i),
+        T   => gpio_oen(6+i));
+
+    cmp_buf_fmc1 : IOBUFDS
+      generic map (
+        DIFF_TERM    => true,
+        IBUF_LOW_PWR => true,
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O   => gpio_in(34+6 + i),
+        IO  => fmc1_la_p_b(i),
+        IOB => fmc1_la_n_b(i),
+        I   => gpio_out(34+6+i),
+        T   => gpio_oen(34+6+i));
+
+
+  end generate gen_fmc_iobufs;
+
+  gen_p2_iobufs : for i in 0 to 19 generate
+
+    cmp_buf_p2 : IOBUFDS
+      generic map (
+        DIFF_TERM    => true,
+        IBUF_LOW_PWR => true,
+        IOSTANDARD   => "DEFAULT")
+      port map (
+        O   => gpio_in(34+34+6 + i),
+        IO  => p2_p_b(i),
+        IOB => p2_n_b(i),
+        I   => gpio_out(34+34+6+i),
+        T   => gpio_oen(34+34+6+i));
+
+  end generate gen_p2_iobufs;
+
+  gpio_in(128 + 0) <= fp_pushbutton_n_i;
+  gpio_in(128 + 1) <= fmc0_pg_i;
+
+  fmc0_tck_o     <= gpio_out(128+2);
+  fmc0_tms_o     <= gpio_out(128 + 3);
+  fmc0_tdi_o     <= gpio_out(128 + 4);
+  gpio_in(128+5) <= fmc0_tdo_i;
+
+
+  gpio_in(128+6) <= fmc1_pg_i;
+
+  fmc1_tck_o        <= gpio_out(128 + 7);
+  fmc1_tms_o        <= gpio_out(128 + 8);
+  fmc1_tdi_o        <= gpio_out(128 + 9);
+  gpio_in(128 + 10) <= fmc1_tdo_i;
+
+
+  si57x_scl_b  <= gpio_out(128 + 11);
+  si57x_sda_b  <= gpio_out(128 + 12);
+  si57x_oe_o   <= gpio_out(128 + 13);
+  si57x_tune_o <= gpio_out(128 + 14);
+
+
+  cmp_clock_mon: entity work.xwb_clock_monitor
+    generic map (
+      g_num_clocks => 6)
+    port map (
+      rst_n_i   => rst_sys_62m5_n,
+      clk_sys_i => clk_sys_62m5,
+      clk_in_i(0) => clk_fpga2,
+      clk_in_i(1) => clk_si57x,
+      clk_in_i(2) => fmc0_clk(0),
+      clk_in_i(3) => fmc0_clk(1),
+      clk_in_i(4) => fmc1_clk(0),
+      clk_in_i(5) => fmc1_clk(1),
+      
+      pps_p1_i  => pps,
+      slave_i   => cnx_slave_in(c_WB_SLAVE_CLOCK_MON),
+      slave_o   => cnx_slave_out(c_WB_SLAVE_CLOCK_MON));
+
+  
+end architecture arch;