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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
aecdf57f
Commit
aecdf57f
authored
Oct 15, 2019
by
Tomasz Wlostowski
1
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svec_base_wr: added DDMTD clock output
parent
410df44d
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14 additions
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6 deletions
+14
-6
svec_base_wr.vhd
hdl/rtl/svec_base_wr.vhd
+14
-6
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hdl/rtl/svec_base_wr.vhd
View file @
aecdf57f
...
...
@@ -271,6 +271,9 @@ entity svec_base_wr is
clk_ref_125m_o
:
out
std_logic
;
rst_ref_125m_n_o
:
out
std_logic
;
-- 125 MHz DDMTD clock output
clk_dmtd_125m_o
:
out
std_logic
;
-- Interrupts
irq_user_i
:
in
std_logic_vector
(
g_NUM_USER_IRQ
+
5
downto
6
)
:
=
(
others
=>
'0'
);
...
...
@@ -362,7 +365,7 @@ architecture top of svec_base_wr is
signal
csr_ddr4_data_wack
:
std_logic
;
signal
csr_ddr4_data_rack
:
std_logic
;
--
--
signal
ddr4_read_ip
:
std_logic
;
signal
ddr4_write_ip
:
std_logic
;
...
...
@@ -401,7 +404,7 @@ architecture top of svec_base_wr is
signal
vme_ga
:
std_logic_vector
(
5
downto
0
);
signal
vme_berr_n
:
std_logic
;
signal
vme_irq_n
:
std_logic_vector
(
7
downto
1
);
-- The wishbone bus to the carrier part.
signal
carrier_wb_out
:
t_wishbone_slave_out
;
signal
carrier_wb_in
:
t_wishbone_slave_in
;
...
...
@@ -469,6 +472,8 @@ architecture top of svec_base_wr is
signal
sfp_scl_in
:
std_logic
;
signal
sfp_scl_out
:
std_logic
;
signal
clk_dmtd_125m
:
std_logic
;
attribute
keep
:
string
;
attribute
keep
of
clk_sys_62m5
:
signal
is
"TRUE"
;
attribute
keep
of
clk_ref_125m
:
signal
is
"TRUE"
;
...
...
@@ -588,7 +593,7 @@ begin -- architecture top
csr_ddr4_addr_i
=>
csr_ddr4_addr
,
csr_ddr4_addr_o
=>
csr_ddr4_addr_out
,
csr_ddr4_addr_wr_o
=>
csr_ddr4_addr_wr
,
-- data to read or to write in ddr4
csr_ddr4_data_i
=>
csr_ddr4_data_in
,
csr_ddr4_data_o
=>
csr_ddr4_data_out
,
...
...
@@ -608,7 +613,7 @@ begin -- architecture top
csr_ddr5_data_rd_o
=>
csr_ddr5_data_rd
,
csr_ddr5_data_wack_i
=>
csr_ddr5_data_wack
,
csr_ddr5_data_rack_i
=>
csr_ddr5_data_rack
,
-- Thermometer and unique id
therm_id_i
=>
therm_id_in
,
therm_id_o
=>
therm_id_out
,
...
...
@@ -840,6 +845,7 @@ begin -- architecture top
clk_sys_62m5_o
=>
clk_sys_62m5
,
clk_ref_125m_o
=>
clk_ref_125m
,
clk_pll_aux_o
=>
clk_pll_aux
,
clk_dmtd_125m_o
=>
clk_dmtd_125m
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
rst_ref_125m_n_o
=>
rst_ref_125m_n
,
rst_pll_aux_n_o
=>
rst_pll_aux_n
,
...
...
@@ -1423,8 +1429,8 @@ begin -- architecture top
ddr5_wr_fifo_empty_o
<=
'0'
;
csr_ddr5_addr
<=
x"0000_0000"
;
ddr5_wb_out
<=
(
adr
=>
(
others
=>
'X'
),
cyc
=>
'0'
,
stb
=>
'0'
,
sel
=>
x"0"
,
we
=>
'0'
,
dat
=>
(
others
=>
'X'
));
ddr5_wb_out
<=
(
adr
=>
(
others
=>
'X'
),
cyc
=>
'0'
,
stb
=>
'0'
,
sel
=>
x"0"
,
we
=>
'0'
,
dat
=>
(
others
=>
'X'
));
csr_ddr5_data_in
<=
x"0000_0000"
;
csr_ddr5_data_rack
<=
csr_ddr5_data_rd
;
csr_ddr5_data_wack
<=
csr_ddr5_data_wr
;
...
...
@@ -1433,4 +1439,6 @@ begin -- architecture top
ddr5_wb_o
.
err
<=
'0'
;
ddr5_wb_o
.
rty
<=
'0'
;
clk_dmtd_125m_o
<=
clk_dmtd_125m
;
end
architecture
top
;
Federico Vaga
@FedericoVaga
mentioned in commit
e22f3709
·
May 20, 2020
mentioned in commit
e22f3709
mentioned in commit e22f3709dc9b73ebe5cf324f0b718eea802b0cba
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