VHDL : test for synchronization with CLK_SR ; doesn't worked

On branch synchronize modified: fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs modified: fpga/sources/src_PLL/PLL_lib.vhdl modified: fpga/sources/src_PLL/PLL_synchronize.vhdl modified: fpga/sources/src_PLL/PLL_top.vhdl

VHDL : test for synchronization with CLK_SR ; doesn't worked
On branch synchronize modified: fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs modified: fpga/sources/src_PLL/PLL_lib.vhdl modified: fpga/sources/src_PLL/PLL_synchronize.vhdl modified: fpga/sources/src_PLL/PLL_top.vhdl
9ad45d02 · Jean-Paul Ricaud · 3d04d885 · 9ad45d02 · 9ad45d02 · 9ad45d02
Commit 9ad45d02 authored Mar 02, 2018 by Jean-Paul Ricaud
4 changed files
--- a/fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
+++ b/fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
--- a/fpga/sources/src_PLL/PLL_lib.vhdl
+++ b/fpga/sources/src_PLL/PLL_lib.vhdl
@@ -7,7 +7,7 @@
 -- File     : PLL_lib.vhdl
 -- Revision : x.x.x
 -- Created  : August 9, 2016
-- Updated  : March 01, 2018
+-- Updated  : March 02, 2018
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -48,14 +48,16 @@ package PLL_lib is

  constant c_PLL_reg_configuration : PLL_register_array := (
    X"00000017", -- R7
-    X"0000008D", -- R13
+--    X"0000008D", -- R13
+    X"000000CD", -- R13
    X"0000001C", -- R12
    X"28001409", -- R9
 --    X"0111CF88", -- R8 ; fixed frequency temperature compensation 24
    X"0111CE48", -- R8 ; frequency temperature compensation 4
-    X"001F3366", -- R6 ; Enout enabled
+--    X"001F3366", -- R6 ; Enout enabled
+    X"001FBB76", -- R6 ; Enout enabled
    X"A0000005", -- R5
-    X"12001FF4", -- R4 ; OSCin freq for 255 MHz and higer ; bypass mode ; R3 = 200R ; R4 = 200R ; C3 = 5pF ; C4 = 5pF
+    X"12001FF4", -- R4 ; OSCin freq for 255 MHz and higer ; VCO_DIV = bypass mode ; R3 = 200R ; R4 = 200R ; C3 = 5pF ; C4 = 5pF
    X"00387F03", -- R3 ; full mode ; charge pump 32x ; digital lock detect ; negative CPP ; doubler = 1 ; 3 order filter ; DITh weak
    X"04000052", -- R2
    X"000000B1", -- R1 ; R = 11

--- a/fpga/sources/src_PLL/PLL_synchronize.vhdl
+++ b/fpga/sources/src_PLL/PLL_synchronize.vhdl
@@ -10,7 +10,7 @@
 -- File     : PLL_synchronize.vhd
 -- Revision : x.x.x
 -- Created  : February 21, 2018
-- Updated  : March 01, 2018
+-- Updated  : March 02, 2018
 --------------------------------------------------------------------------------
 -- Author       : Jean-Paul Ricaud
 -- Organization : Synchrotron Soleil
@@ -63,7 +63,8 @@ architecture rtl_PLL_synchronize of PLL_synchronize is
  -- constant
  ------------------------------------------------------------------------------
 --  constant c_cntmax : unsigned (2 downto 0) := "110"; -- #3 MHz
-  constant c_cntmax : unsigned (31 downto 0) := X"08FFFFFF";
+--  constant c_cntmax : unsigned (31 downto 0) := X"01FFFFFF";
+  constant c_cntmax : unsigned (31 downto 0) := X"00000006";

  ------------------------------------------------------------------------------
  -- signal

--- a/fpga/sources/src_PLL/PLL_top.vhdl
+++ b/fpga/sources/src_PLL/PLL_top.vhdl
@@ -155,8 +155,8 @@ architecture rtl_PLL_top of PLL_top is

  calibartion_PLL : entity work.PLL_calibration (rtl_PLL_calibration)
    generic map (
-      g_registers       => c_PLL_reg_calibration,
-      g_registers_size  => c_PLL_reg_calibration'HIGH )
+      g_registers      => c_PLL_reg_calibration,
+      g_registers_size => c_PLL_reg_calibration'HIGH )
    port map (
      p_clkin         => p_clkin,
      p_reset         => s_recalibrate,
@@ -174,13 +174,13 @@ architecture rtl_PLL_top of PLL_top is
  ------------------------------------------------------------------------------
  ------------------------------------------------------------------------------
  s_PLL_ENout <= s_PLL_ENout_config and s_PLL_ENout_calib;
-  p_PLL_LE    <= s_PLL_LE_config    or s_PLL_LE_calib;
-  p_PLL_CLK   <= s_PLL_CLK_config   or s_PLL_CLK_calib;
-  p_PLL_DATA  <= s_PLL_DATA_config  or s_PLL_DATA_calib;
-  p_PLL_ENA   <= s_PLL_ENA_config   or s_PLL_ENA_calib;
-  p_PLL_ENB   <= s_PLL_ENB_config   or s_PLL_ENB_calib;
-  p_PLL_ENC   <= s_PLL_ENC_config   or s_PLL_ENC_calib;
-  p_PLL_END   <= s_PLL_END_config   or s_PLL_END_calib;
+  p_PLL_LE    <= s_PLL_LE_config    or  s_PLL_LE_calib;
+  p_PLL_CLK   <= s_PLL_CLK_config   or  s_PLL_CLK_calib;
+  p_PLL_DATA  <= s_PLL_DATA_config  or  s_PLL_DATA_calib;
+  p_PLL_ENA   <= s_PLL_ENA_config   or  s_PLL_ENA_calib;
+  p_PLL_ENB   <= s_PLL_ENB_config   or  s_PLL_ENB_calib;
+  p_PLL_ENC   <= s_PLL_ENC_config   or  s_PLL_ENC_calib;
+  p_PLL_END   <= s_PLL_END_config   or  s_PLL_END_calib;

  with p_SW select
    p_PLL_ENout <=