On branch master

	modified:   README.md

 On branch master

	modified:   README.md

 On branch master

	modified:   licenses/licence.txt

 On branch development

	new file:   documentation/source/img/front_face_TLK33.jpg
	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	new file:   fpga/sources/testbench/pll_sync_tb.vhdl

 On branch development

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	modified:   fpga/sources/src_PLL/PLL_synchronize.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl

 On branch development

	modified:   documentation/source/cfg_peltier.rst

 On branch development

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs

added a synchro reset after PLL configuration or recalibration to be
able to reset external divider (TBD)

 On branch synchronize

	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	modified:   fpga/sources/src_IOs/IOs_top.vhdl
	modified:   fpga/sources/src_PLL/PLL_calibration.vhdl
	modified:   fpga/sources/src_PLL/PLL_configuration.vhdl
	modified:   fpga/sources/src_PLL/PLL_synchronize.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl
	modified:   fpga/sources/top.vhdl

 On branch synchronize

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_PLL/PLL_lib.vhdl
	modified:   fpga/sources/src_PLL/PLL_synchronize.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl

On branch synchronize

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	modified:   fpga/sources/src_IOs/IOs_top.vhdl
	modified:   fpga/sources/src_PLL/PLL_lib.vhdl
	modified:   fpga/sources/src_PLL/PLL_synchronize.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl
	modified:   fpga/sources/testbench/pll_top_tb.vhdl
	modified:   fpga/sources/top.vhdl

synchronization to calibration file

 On branch synchronize

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_PLL/PLL_calibration.vhdl
	modified:   fpga/sources/src_PLL/PLL_configuration.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl
	renamed:    fpga/TimIQ/top.ucf -> fpga/sources/top.ucf

the laser trigger

 On branch synchronize

	modified:   fpga/sources/src_PLL/PLL_configuration.vhdl
	modified:   fpga/sources/src_PLL/PLL_synchronize.vhdl
	modified:   fpga/sources/src_PLL/PLL_top.vhdl

the laser trigger signal by disabling and enabling the PLL
output synchronouly with the triger signal

 On branch synchronize

	modified:   fpga/sources/src_PLL/PLL_debounce.vhdl
	new file:   fpga/sources/src_PLL/PLL_synchronize.vhdl

 On branch development
	modified:   fpga/sources/src_PLL/PLL_top.vhdl

 On branch development

	modified:   documentation/source/cfg_frequency_divider.rst

 On branch development

	new file:   documentation/source/cfg_frequency_divider.rst
	new file:   documentation/source/img/FPGA_switch.png
	modified:   documentation/source/index.rst
	modified:   fpga/sources/src_PLL/PLL_top.vhdl

the FPGA board:

SW5 | SW4 | SW3 | SW2 | SW1 | SW0 ||
 0  |  0  |  0  |  0  |  0  |  0  || division by 1  (3 GHz) for MAX IV ; no PLL
 0  |  0  |  0  |  0  |  0  |  1  || division by 1  (2.8 GHz) ; with PLL
 0  |  0  |  0  |  0  |  1  |  0  || division by 8  (352 MHz) ; TEMPO
 0  |  0  |  0  |  0  |  1  |  1  || division by 32 (88 MHz)  ; CRISTAL
 0  |  0  |  0  |  1  |  0  |  0  || division by 64 (44 MHz)  ; ODE

 On branch development

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl
	modified:   fpga/sources/top.vhdl

 On branch development

	modified:   fpga/sources/src_Freqdividers/FreqDividers_top.vhdl

right LEDs description

 On branch development

	modified:   documentation/source/cfg_peltier.rst
	modified:   documentation/source/error_network.rst
	modified:   documentation/source/error_trouble_diagnostic.rst
	modified:   documentation/source/fct_LEDs.rst
	modified:   documentation/source/note_flashing_CPU.rst
	modified:   documentation/source/note_temp_read_write.rst
	modified:   documentation/source/state_PLL_unlocked_soleil.rst
	modified:   documentation/source/state_up_warming.rst

 On branch development

	modified:   soft/test_local_CPU_access.py

 On branch development

	modified:   documentation/source/cfg_peltier.rst
	modified:   documentation/source/error_network.rst
	modified:   documentation/source/error_trouble_diagnostic.rst

 On branch development

	modified:   version.txt

 On branch development

	modified:   soft/www/web_settings.wsgi

 On branch test_I2C_access

	modified:   soft/test_local_CPU_access.py

 On branch test_I2C_access

	modified:   script/test_IQ_webserver-stability_MAXIV.py
	modified:   script/test_IQ_webserver-stability_SOLEIL.py
	modified:   soft/test_local_CPU_access.py
	modified:   version.txt

 On branch test_I2C_access

	modified:   script/test_IQ_webserver-stability_MAXIV.py

 On branch test_I2C_access

	modified:   fpga/TimIQ/TimIQ_EEPROM/TimIQ_XCF.mcs
	modified:   fpga/sources/src_BBB/BBB_I2C.vhdl
	new file:   fpga/sources/src_BBB/BBB_wait_state.vhdl

CPU and the FPGA

 On branch test_I2C_access

	new file:   script/start_py.sh
	new file:   soft/test_local_CPU_access.py

 On branch test_I2C_access

	new file:   script/test_IQ_webserver-MAXIV.py
	new file:   script/test_IQ_webserver-SOLEIL.py
	new file:   script/test_IQ_webserver-stability_MAXIV.py
	new file:   script/test_IQ_webserver-stability_SOLEIL.py

 On branch test_I2C_access

	deleted:    script/IQ_parameters.py
	deleted:    script/get_V.py
	deleted:    script/input_IQ-2.py
	deleted:    script/input_IQ.py
	deleted:    script/read_urllib.py
	deleted:    script/send_urllib.py
	deleted:    script/set_IQ.py
	deleted:    script/start_py.sh
	deleted:    script/test_IQ.py
	deleted:    script/test_IQ_drift.py
	deleted:    script/test_IQ_webserver.py
	modified:   soft/set_IQ.py
	modified:   soft/www/set_iValue.wsgi
	modified:   soft/www/set_qValue.wsgi

 On branch test_I2C_access

	modified:   soft/get_V.py
	modified:   soft/set_IQ.py

 On branch test_I2C_access

	modified:   soft/get_V.py

   using file system insted of SMBUS library

 On branch test_I2C_access

	modified:   soft/get_V.py

 On branch development

	new file:   version.txt