Commits · hydra · Projects / urv-core · Open Hardware Repository

09 Dec, 2020 1 commit
- modifications for hydra · 48681306
  Mattia Rizzi authored Dec 09, 2020
```
Signed-off-by: Mattia Rizzi <mattia.rizzi@cern.ch>
```
  48681306
20 Mar, 2019 4 commits
- Add sw/test_irq. · 193f15db
  Tristan Gingold authored Mar 20, 2019
  
  193f15db
- adjust tb. · f3cf9ecd
  Tristan Gingold authored Mar 20, 2019
  
  f3cf9ecd
- sw: add a makefile rule for genraminit · ce5fd7cf
  Tristan Gingold authored Mar 20, 2019
  
  ce5fd7cf
- urv: add mpie, restore on mret. · c776e4c1
  Tristan Gingold authored Mar 20, 2019
  
  c776e4c1
19 Mar, 2019 5 commits
- tb/cpu: add a reg to generate irqs. · 9e186e33
  Tristan Gingold authored Mar 19, 2019
  
  9e186e33
- main.c: get rid of warnings. · b6c952af
  Tristan Gingold authored Mar 19, 2019
  
  b6c952af
- urv: handle irq using v1.10 spec. · 180ec3e9
  Tristan Gingold authored Mar 19, 2019
  
  180ec3e9
- urv_exec: minor refactoring. · e2859cda
  Tristan Gingold authored Mar 19, 2019
  
  e2859cda
- tb/cpu: update (remove dm_ready). · 3bb403fb
  Tristan Gingold authored Mar 19, 2019
  
  3bb403fb
31 Jan, 2019 8 commits
- Update MIMPID. · 5c7e906c
  Tristan Gingold authored Jan 31, 2019
  
  5c7e906c
- urv_cpu.v: add a comment about data memory interface. · 56af5885
  Tristan Gingold authored Jan 31, 2019
  
  56af5885
- remove dm_ready_i (was unused and not working). · 788f6a59
  Tristan Gingold authored Jan 31, 2019
  
  788f6a59
- urv_cpu.v: minor reformatting. · f2a42195
  Tristan Gingold authored Jan 31, 2019
  
  f2a42195
- urv_exec.v: minor refactoring. · e45c986f
  Tristan Gingold authored Jan 31, 2019
  
  e45c986f
- isa-testsuite: update waves. · e3938987
  Tristan Gingold authored Jan 31, 2019
  
  e3938987
- isa-testsuite: add a test with memory wait state. · 2f19be55
  Tristan Gingold authored Jan 31, 2019
  
  2f19be55
- urv_exec.v: fix to allow data memory wait state. · e4e81fad
  Tristan Gingold authored Jan 31, 2019
  
  e4e81fad
30 Jan, 2019 2 commits
- isa-testsuite: adjust waves. · 59b9c3ad
  Tristan Gingold authored Jan 30, 2019
  
  59b9c3ad
- isa-testsuite/main.sv: reduce number of tests. · dba5b08e
  Tristan Gingold authored Jan 30, 2019
  
  dba5b08e
28 Jan, 2019 1 commit
- urv: add MIMPID. · 22ee94a4
  Tristan Gingold authored Jan 28, 2019
  
  22ee94a4
25 Jan, 2019 1 commit
- debug/main.sv: adjust after changes in urv_cpu · 773694b6
  Tristan Gingold authored Jan 25, 2019
  
  773694b6
13 Nov, 2018 3 commits
- core: fixed unwanted destination register write when a MUL instruction is… · 4db75631
  Tomasz Wlostowski authored Nov 13, 2018
```
core: fixed unwanted destination register write when a MUL instruction is followed by a stalling instruction
```
  4db75631
- core: more accurate multiply instruction detection in the decoder · d7bc65d4
  Tomasz Wlostowski authored Nov 13, 2018
  
  d7bc65d4
- testsuite: test for mul->mulhu incorrect RD write · f64df50e
  Tomasz Wlostowski authored Nov 13, 2018
  
  f64df50e
17 Jul, 2018 3 commits
- Remove some trailing whitespaces. · 70e9e78f
  Tristan Gingold authored Jul 17, 2018
  
  70e9e78f
- Fix g_with_hw_debug propagation. · 018f9e61
  Tristan Gingold authored Jul 17, 2018
  
  018f9e61
- rtl: update all licenses to solderpad 2 (for files used by MT/masterFIP) · c2d4f0ce
  Dimitris Lampridis authored Jun 08, 2018
  
  c2d4f0ce
08 Jun, 2018 1 commit
- rtl: update all licenses to solderpad 2 (for files used by MT/masterFIP) · 890dfda6
  Dimitris Lampridis authored Jun 08, 2018
  
  890dfda6
05 Jun, 2018 2 commits
- rtl: stall register file on pipeline stall too · 4d6e4c92
  Tomasz Wlostowski authored Jun 05, 2018
  
  4d6e4c92
- rtl: default values for parameters, removed blocking assignments (synthesis fixes) · 261d6b36
  Tomasz Wlostowski authored Jun 05, 2018
  
  261d6b36
21 Apr, 2018 3 commits
- tb: automatized ISA testbench (for all feature variants), initial version · 5cffb670
  Tomasz Wlostowski authored Apr 21, 2018
  
  5cffb670
- sw: correctly emulate divide-by-zero case · ecc50e05
  Tomasz Wlostowski authored Apr 21, 2018
  
  ecc50e05
- RTL: proper support for hardware multiply/divide, including correct divide-by-zero handling. · 49cb85d2
  Tomasz Wlostowski authored Apr 21, 2018
  
  49cb85d2
09 Apr, 2018 1 commit
- rtl: added optional hardware division and multiply-high instruction · a215404d
  Tomasz Wlostowski authored Apr 09, 2018
  
  a215404d
19 Mar, 2018 5 commits
- Run isa testsuite. · 91e88f93
  Tristan Gingold authored Mar 19, 2018
  
  91e88f93
- Remove unused signals, fix some warnings. · 2cf284ed
  Tristan Gingold authored Mar 19, 2018
  
  2cf284ed
- Simplify debug interface. · 134759b2
  Tristan Gingold authored Mar 19, 2018
  
  134759b2
- Minor clean-up. · c701e7ca
  Tristan Gingold authored Mar 19, 2018
  
  c701e7ca
- hdl: disable unused d_is_divide_i port (for now) · 44d69a62
  Dimitris Lampridis authored Mar 19, 2018
  
  44d69a62