Commit 712f07b1 authored by Dimitris Lampridis's avatar Dimitris Lampridis

sw/tools/wrc: cleanup rellocation function

parent f1b55890
......@@ -71,27 +71,8 @@ void _vfchd_print_usage(const char *progname)
int _vfchd_vme64x_rellocate(struct vfchd_dev *dev)
{
int i;
// Simple hard-coded values which declare two functions
// for A24 and A32 accesses.
const uint32_t vme64x_relloc_seq_addr[] =
{
0x7fff8, 0x7fff4, 0x7ff30, 0x7ff5c,
0x7ff58, 0x7ff60, 0x7ff64, 0x7ff68,
0x7ff6c, 0x7ff70, 0x7ff74, 0x7ff78,
0x7ff7c, 0x7fff8
};
const uint8_t vme64x_relloc_seq_data[] =
{
0x80, 0x10, 0x01, 0x00,
0x00, 0x04, 0x00, 0x00,
0x24, 0x00, 0x20, 0x00,
0xe4, 0x10
};
/* temporary map, will be discarded at the end of the
rellocation function */
dev->map.am = VME_CR_CSR;
dev->map.data_width = VME_D32;
dev->map.sizel = 0x80000;
......@@ -103,11 +84,36 @@ int _vfchd_vme64x_rellocate(struct vfchd_dev *dev)
return -1;
}
for (i = 0; i < 14; i++) {
_vfchd_writel(dev,
vme64x_relloc_seq_data[i],
vme64x_relloc_seq_addr[i]);
}
/* reset the core */
_vfchd_writel(dev, RESET_CORE, BIT_SET_REG);
usleep(10000);
/* disable the core */
_vfchd_writel(dev, ENABLE_CORE, BIT_CLR_REG);
/* default to 32bit WB interface */
_vfchd_writel(dev, WB32, WB_32_64);
/* set interrupt vector and level */
_vfchd_writel(dev, 0, INTVECTOR);
_vfchd_writel(dev, 0, INT_LEVEL);
/* FUNCTION0 for A32 (dev->slot << 24) */
_vfchd_writel(dev, dev->slot & 0xff, FUN0ADER);
_vfchd_writel(dev, (dev->slot << 8) & 0xff, FUN0ADER + 4);
_vfchd_writel(dev, (dev->slot << 16) & 0xff, FUN0ADER + 8);
_vfchd_writel(dev, (VME_A32_USER_DATA_SCT & 0x3f) << 2,
FUN0ADER + 12);
/* FUNCTION1 for A24 (dev->slot << 19) */
_vfchd_writel(dev, (dev->slot >> 5) & 0xff, FUN1ADER);
_vfchd_writel(dev, (dev->slot << 3) & 0xff, FUN1ADER + 4);
_vfchd_writel(dev, (dev->slot << 11) & 0xff, FUN1ADER + 8);
_vfchd_writel(dev, (VME_A24_USER_DATA_SCT & 0x3f) << 2,
FUN1ADER + 12);
/* enable module, hence make FUN0/1 available */
_vfchd_writel(dev, ENABLE_CORE, BIT_SET_REG);
vme_unmap(&(dev->map), 1);
......
......@@ -12,6 +12,18 @@
#define VFCHD_WRC_SYSCON_DEFAULT 0x20400
#define VFCHD_WRC_VUART_DEFAULT 0x20500
/* VFCHD CSR offsets */
#define FUN0ADER 0x7FF60
#define FUN1ADER 0x7FF70
#define INT_LEVEL 0x7ff58
#define INTVECTOR 0x7ff5c
#define WB_32_64 0x7ff30
#define BIT_SET_REG 0x7FFF8
#define BIT_CLR_REG 0x7FFF4
#define WB32 1
#define RESET_CORE 0x80
#define ENABLE_CORE 0x10
struct vfchd_dev {
uint32_t wrc_base_offset;
uint32_t wrc_mem_base;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment