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VME SBC A25 PCIe to VME bridge
Commit 27402512 authored by Tristan Gingold's avatar Tristan Gingold
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16z091-01_src: simplify rx_module.vhd

parent d4336cff
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Showing with 8 additions and 17 deletions
hdl/16z091-01_src/Source/rx_module.vhd
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......@@ -117,15 +117,11 @@ signal int_fifo_action_done : std_logic;
-- FIFO signals
signal int_c_wr_enable : std_logic;
signal int_c_wr_full : std_logic;
signal int_rx_wrusedw_c : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_c_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_c_usedw : std_logic_vector(9 downto 0);
signal int_rx_fifo_c_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_wr_wr_enable : std_logic;
signal int_wr_wr_full : std_logic;
signal int_rx_wrusedw_wr : std_logic_vector(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_wrusedw_wr_temp : std_logic_vector(9 downto 0);
signal int_rx_fifo_wr_usedw : std_logic_vector(9 downto 0);
signal int_rx_fifo_wr_usedw : unsigned(RX_LPM_WIDTHU-1 downto 0);
signal int_rx_fifo_data : std_logic_vector(63 downto 0);
......@@ -150,11 +146,6 @@ begin
rx_st_mask0 <= '0';
rx_st_ready0 <= int_ready;
int_rx_wrusedw_c_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_c)),10));
int_rx_wrusedw_wr_temp <= std_logic_vector(to_unsigned(to_integer(unsigned(int_rx_wrusedw_wr)),10));
int_rx_fifo_c_usedw <= int_rx_wrusedw_c_temp;
int_rx_fifo_wr_usedw <= int_rx_wrusedw_wr_temp;
-- +----------------------------------------------------------------------------
-- | process section
-- +----------------------------------------------------------------------------
......@@ -211,14 +202,14 @@ begin
-- else deassert it until the FIFOs are not full
-------------------------------------------------------
if ((int_err = '1' or rx_st_err0 = '1') and rx_st_eop0 = '1' and rx_st_valid0 = '1') or
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw >= FIFO_MAX_USEDW) or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw >= FIFO_MAX_USEDW) then
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw >= unsigned(FIFO_MAX_USEDW)) or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw >= unsigned(FIFO_MAX_USEDW)) then
int_ready <= '0';
elsif int_err = '0' and (
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw < FIFO_MAX_USEDW and int_c_wr_full = '0') or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw < FIFO_MAX_USEDW and int_wr_wr_full = '0')
(int_tlp_type = TYPE_IS_CPL and int_rx_fifo_c_usedw < unsigned(FIFO_MAX_USEDW) and int_c_wr_full = '0') or
(int_tlp_type /= TYPE_IS_CPL and int_rx_fifo_wr_usedw < unsigned(FIFO_MAX_USEDW) and int_wr_wr_full = '0')
) then
int_ready <= '1';
......@@ -318,7 +309,7 @@ begin
q => rx_fifo_c_out,
rdempty => rx_fifo_c_empty,
wrfull => int_c_wr_full,
wrusedw => int_rx_wrusedw_c);
unsigned(wrusedw) => int_rx_fifo_c_usedw);
-- MEM or IO TLP, read by wb master
wr_fifo_comp : entity work.generic_dcfifo_mixedw
......@@ -340,7 +331,7 @@ begin
q => rx_fifo_wr_out,
rdempty => rx_fifo_wr_empty,
wrfull => int_wr_wr_full,
wrusedw => int_rx_wrusedw_wr);
unsigned(wrusedw) => int_rx_fifo_wr_usedw);
-------------------------
-- manage debug signals
......
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