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VME SBC A25 PCIe to VME bridge
Commits
d4336cff
Commit
d4336cff
authored
Jan 16, 2024
by
Tristan Gingold
Committed by
Tristan Gingold
Jan 16, 2024
Browse files
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Plain Diff
Simplify hdl
Remove components, add comments, fix sensitivity
parent
b6f5fc93
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Showing
7 changed files
with
67 additions
and
190 deletions
+67
-190
init.vhd
hdl/16z091-01_src/Source/init.vhd
+1
-0
ip_16z091_01.vhd
hdl/16z091-01_src/Source/ip_16z091_01.vhd
+3
-3
rx_ctrl.vhd
hdl/16z091-01_src/Source/rx_ctrl.vhd
+2
-22
rx_module.vhd
hdl/16z091-01_src/Source/rx_module.vhd
+2
-10
tx_put_data.vhd
hdl/16z091-01_src/Source/tx_put_data.vhd
+1
-3
wbmon.vhd
hdl/16z100-00_src/Source/wbmon.vhd
+17
-36
wb_bus.vhd
hdl/top/wb_bus.vhd
+41
-116
No files found.
hdl/16z091-01_src/Source/init.vhd
View file @
d4336cff
...
...
@@ -105,6 +105,7 @@ begin
elsif
(
core_clk
'event
and
core_clk
=
'1'
)
then
tl_cfg_ctl_wr_q
<=
tl_cfg_ctl_wr
;
-- Sample the interesting values when tl_cfg_ctl_wr toggles.
if
(((
tl_cfg_ctl_wr
=
'1'
and
tl_cfg_ctl_wr_q
=
'0'
)
or
(
tl_cfg_ctl_wr
=
'0'
and
tl_cfg_ctl_wr_q
=
'1'
))
and
(
tl_cfg_add
=
x"0"
or
tl_cfg_add
=
x"D"
or
tl_cfg_add
=
x"F"
)
)
then
sample
<=
'1'
;
...
...
hdl/16z091-01_src/Source/ip_16z091_01.vhd
View file @
d4336cff
...
...
@@ -479,19 +479,19 @@ begin
wbs_err
=>
wbs_err
,
wbs_dat_o
=>
wbs_dat_o
,
-- Rx Module
-- Rx Module
(completion)
rx_fifo_c_empty
=>
rx_fifo_c_empty_int
,
rx_fifo_c_out
=>
rx_fifo_c_out_int
,
rx_fifo_c_rd_enable
=>
rx_fifo_c_rd_enable_int
,
-- Tx Module
tx_fifo_wr_head_full
=>
tx_fifo_wr_head_full_int
,
tx_fifo_w_data_full
=>
tx_fifo_w_data_full_int
,
tx_fifo_w_data_usedw
=>
tx_fifo_w_data_usedw_int
,
tx_fifo_wr_head_usedw
=>
tx_fifo_wr_head_usedw_int
,
tx_fifo_wr_head_clr
=>
tx_fifo_wr_head_clr_int
,
tx_fifo_wr_head_enable
=>
tx_fifo_wr_head_enable_int
,
tx_fifo_wr_head_in
=>
tx_fifo_wr_head_in_int
,
tx_fifo_w_data_full
=>
tx_fifo_w_data_full_int
,
tx_fifo_w_data_usedw
=>
tx_fifo_w_data_usedw_int
,
tx_fifo_w_data_clr
=>
tx_fifo_w_data_clr_int
,
tx_fifo_w_data_enable
=>
tx_fifo_w_data_enable_int
,
tx_fifo_w_data_in
=>
tx_fifo_w_data_in_int
,
...
...
hdl/16z091-01_src/Source/rx_ctrl.vhd
View file @
d4336cff
...
...
@@ -65,7 +65,6 @@ entity rx_ctrl is
rx_fifo_wr_enable_o
:
out
std_logic
;
-- rx_sig_manage
sop_q_i
:
in
std_logic
;
fifo_action_done_o
:
out
std_logic
;
-- rx_get_data
...
...
@@ -84,25 +83,6 @@ architecture rx_ctrl_arch of rx_ctrl is
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component
rx_len_cntr
port
(
clk_i
:
in
std_logic
;
rst_i
:
in
std_logic
;
-- rx_get_data
load_cntr_val_i
:
in
std_logic_vector
(
9
downto
0
);
-- rx_ctrl
load_cntr_i
:
in
std_logic
;
enable_cntr_i
:
in
std_logic
;
len2fifo_o
:
out
std_logic_vector
(
9
downto
0
)
);
end
component
;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
...
...
@@ -450,7 +430,7 @@ begin
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
c_len_cntr_comp
:
rx_len_cntr
c_len_cntr_comp
:
entity
work
.
rx_len_cntr
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
...
...
@@ -464,7 +444,7 @@ begin
len2fifo_o
=>
int_len2fifo_c
);
wr_len_cntr_comp
:
rx_len_cntr
wr_len_cntr_comp
:
entity
work
.
rx_len_cntr
port
map
(
clk_i
=>
clk_i
,
rst_i
=>
rst_i
,
...
...
hdl/16z091-01_src/Source/rx_module.vhd
View file @
d4336cff
...
...
@@ -131,7 +131,6 @@ signal int_rx_fifo_data : std_logic_vector(63 downto 0);
-- signals for signal management process
signal
int_ready
:
std_logic
;
signal
int_sop
:
std_logic
;
signal
int_err
:
std_logic
;
signal
int_sop_q
:
std_logic
;
signal
int_tlp_type
:
std_logic_vector
(
4
downto
0
);
...
...
@@ -187,7 +186,6 @@ begin
begin
if
rst
=
'1'
then
int_ready
<=
'0'
;
int_sop
<=
'0'
;
int_err
<=
'0'
;
int_sop_q
<=
'0'
;
...
...
@@ -239,13 +237,6 @@ begin
int_err
<=
int_err
;
end
if
;
if
rx_st_valid0
=
'1'
and
rx_st_eop0
=
'1'
then
int_sop
<=
'0'
;
elsif
rx_st_valid0
=
'1'
and
rx_st_sop0
=
'1'
then
int_sop
<=
'1'
;
else
int_sop
<=
int_sop
;
end
if
;
end
if
;
end
process
rx_sig_manage
;
...
...
@@ -272,7 +263,6 @@ begin
rx_fifo_wr_enable_o
=>
int_wr_wr_enable
,
-- rx_sig_manage
sop_q_i
=>
int_sop_q
,
fifo_action_done_o
=>
int_fifo_action_done
,
-- rx_get_data
...
...
@@ -308,6 +298,7 @@ begin
);
-- Completion TLP
c_fifo_comp
:
entity
work
.
generic_dcfifo_mixedw
generic
map
(
g_device_family
=>
DEVICE_FAMILY
,
...
...
@@ -329,6 +320,7 @@ begin
wrfull
=>
int_c_wr_full
,
wrusedw
=>
int_rx_wrusedw_c
);
-- MEM or IO TLP, read by wb master
wr_fifo_comp
:
entity
work
.
generic_dcfifo_mixedw
generic
map
(
g_device_family
=>
DEVICE_FAMILY
,
...
...
hdl/16z091-01_src/Source/tx_put_data.vhd
View file @
d4336cff
...
...
@@ -131,8 +131,7 @@ begin
mem_io_int
<=
'0'
;
io_write_int
<=
'0'
;
else
if
(
clk
'event
and
clk
=
'1'
)
then
elsif
(
clk
'event
and
clk
=
'1'
)
then
-- capture data length from appropriate FIFO packet
if
(
get_header
=
'1'
and
c_wrrd
=
'0'
)
then
data_length
<=
tx_c_head_out
(
9
downto
0
);
...
...
@@ -354,7 +353,6 @@ begin
if
(
data_enable
=
'1'
)
then
tx_st_data0
<=
data_qq
;
end
if
;
end
if
;
end
if
;
end
process
data_path
;
...
...
hdl/16z100-00_src/Source/wbmon.vhd
View file @
d4336cff
...
...
@@ -160,28 +160,10 @@ ENTITY wbmon IS
er
:
OUT
std_logic
;
co
:
OUT
std_logic_vector
(
7
DOWNTO
0
)
);
PROCEDURE
outp
(
VARIABLE
e
:
OUT
std_logic
;
VARIABLE
c
:
OUT
std_logic_vector
(
7
DOWNTO
0
);
message
:
string
:
=
"Unknown Error"
;
code
:
std_logic_vector
(
7
DOWNTO
0
):
=
x"FF"
;
enable
:
std_logic
;
sev
:
severity_level
:
=
NOTE
;
condition
:
boolean
:
=
FALSE
);
PROCEDURE
outp_cycle
(
message
:
string
:
=
"Not Defined"
;
sev
:
severity_level
:
=
NOTE
;
adr
:
std_logic_vector
(
31
DOWNTO
0
);
data
:
std_logic_vector
(
31
DOWNTO
0
);
ende
:
string
:
=
"OK"
);
END
wbmon
;
ARCHITECTURE
wbmon_arch
OF
wbmon
IS
function
to_string
function
to_string
(
constant
val
:
in
std_logic_vector
)
return
string
is
...
...
@@ -261,7 +243,7 @@ ARCHITECTURE wbmon_arch OF wbmon IS
END
;
FUNCTION
data_out
(
sel
:
std_logic_vector
(
3
downto
0
);
dat
:
std_logic_vector
(
31
downto
0
))
RETURN
string
IS
FUNCTION
data_out
(
b
sel
:
std_logic_vector
(
3
downto
0
);
dat
:
std_logic_vector
(
31
downto
0
))
RETURN
string
IS
variable
byte0
:
string
(
1
to
2
);
variable
byte1
:
string
(
1
to
2
);
variable
byte2
:
string
(
1
to
2
);
...
...
@@ -269,25 +251,25 @@ ARCHITECTURE wbmon_arch OF wbmon IS
BEGIN
if
sel
(
0
)
=
'1'
then
if
b
sel
(
0
)
=
'1'
then
byte0
:
=
to_hstring
(
8
,
dat
(
7
downto
0
));
else
byte0
:
=
"XX"
;
end
if
;
if
sel
(
1
)
=
'1'
then
if
b
sel
(
1
)
=
'1'
then
byte1
:
=
to_hstring
(
8
,
dat
(
15
downto
8
));
else
byte1
:
=
"XX"
;
end
if
;
if
sel
(
2
)
=
'1'
then
if
b
sel
(
2
)
=
'1'
then
byte2
:
=
to_hstring
(
8
,
dat
(
23
downto
16
));
else
byte2
:
=
"XX"
;
end
if
;
if
sel
(
3
)
=
'1'
then
if
b
sel
(
3
)
=
'1'
then
byte3
:
=
to_hstring
(
8
,
dat
(
31
downto
24
));
else
byte3
:
=
"XX"
;
...
...
@@ -313,7 +295,6 @@ ARCHITECTURE wbmon_arch OF wbmon IS
IS
wbname
&
"_transcript.txt"
;
-- Write- File
VARIABLE
wl
:
line
;
VARIABLE
ol
:
line
;
-- synthesis translate_on
BEGIN
IF
NOT
(
condition
)
AND
enable
=
'1'
THEN
...
...
@@ -342,7 +323,7 @@ ARCHITECTURE wbmon_arch OF wbmon IS
PROCEDURE
outp_cycle
(
message
:
string
:
=
"Not Defined"
;
sev
:
severity_level
:
=
NOTE
;
ad
r
:
std_logic_vector
(
31
DOWNTO
0
);
ad
dr
:
std_logic_vector
(
31
DOWNTO
0
);
data
:
std_logic_vector
(
31
DOWNTO
0
);
ende
:
string
:
=
"OK"
)
IS
...
...
@@ -361,7 +342,7 @@ ARCHITECTURE wbmon_arch OF wbmon IS
WRITE
(
wl
,
") "
&
message
&
" ADR: "
);
-- Output Data
hwrite
(
wl
,
adr
,
justified
=>
left
);
hwrite
(
wl
,
ad
d
r
,
justified
=>
left
);
write
(
wl
,
string
'
(
" SEL: "
));
WRITE
(
wl
,
sel
,
field
=>
4
);
write
(
wl
,
string
'
(
" DATA: "
));
...
...
@@ -417,28 +398,28 @@ enable <= '1';
-- synthesis translate_off
PROCESS
(
clk
)
VARIABLE
burst
:
string
(
1
TO
5
);
VARIABLE
burst
str
:
string
(
1
TO
5
);
BEGIN
IF
rising_edge
(
clk
)
THEN
IF
(
cti
/=
"000"
)
THEN
burst
:
=
"Burst"
;
burst
str
:
=
"Burst"
;
ELSE
burst
:
=
" "
;
burst
str
:
=
" "
;
END
IF
;
IF
(
ack
=
'1'
AND
stb
=
'1'
AND
cyc
=
'1'
)
THEN
-- Output write or read actions
IF
(
we
=
'1'
)
THEN
outp_cycle
(
"Write Cycle "
&
burst
,
NOTE
,
adr
,
sldat_i
,
" --> OK"
);
outp_cycle
(
"Write Cycle "
&
burst
str
,
NOTE
,
adr
,
sldat_i
,
" --> OK"
);
ELSE
outp_cycle
(
"Read Cycle "
&
burst
,
NOTE
,
adr
,
sldat_o
,
" --> OK"
);
outp_cycle
(
"Read Cycle "
&
burst
str
,
NOTE
,
adr
,
sldat_o
,
" --> OK"
);
END
IF
;
END
IF
;
IF
(
err
=
'1'
AND
stb
=
'1'
AND
cyc
=
'1'
)
THEN
-- Output write or read actions
IF
(
we
=
'1'
)
THEN
outp_cycle
(
"Write Cycle "
&
burst
,
NOTE
,
adr
,
sldat_i
,
" --> ERROR"
);
outp_cycle
(
"Write Cycle "
&
burst
str
,
NOTE
,
adr
,
sldat_i
,
" --> ERROR"
);
ELSE
outp_cycle
(
"Read Cycle "
&
burst
,
NOTE
,
adr
,
sldat_o
,
" --> ERROR"
);
outp_cycle
(
"Read Cycle "
&
burst
str
,
NOTE
,
adr
,
sldat_o
,
" --> ERROR"
);
END
IF
;
END
IF
;
END
IF
;
...
...
@@ -446,7 +427,7 @@ enable <= '1';
-- synthesis translate_on
-- Create Cycle start time
PROCESS
(
clk
)
PROCESS
(
clk
,
rst
)
VARIABLE
c
:
std_logic_vector
(
7
DOWNTO
0
);
VARIABLE
e
:
std_logic
;
BEGIN
...
...
@@ -581,7 +562,7 @@ enable <= '1';
-- synthesis translate_off
-- test if signals are 'U', 'Z' or 'X'
PROCESS
(
clk
,
rst
,
cyc
,
stb
,
we
,
ack
,
err
,
cti
,
adr
,
sldat_i
,
sldat_o
)
PROCESS
(
clk
,
rst
,
cyc
,
stb
,
we
,
ack
,
err
,
cti
,
adr
,
sldat_i
,
sldat_o
,
sel
,
enable
)
VARIABLE
c
:
std_logic_vector
(
7
DOWNTO
0
);
VARIABLE
e
:
std_logic
;
BEGIN
...
...
hdl/top/wb_bus.vhd
View file @
d4336cff
...
...
@@ -87,99 +87,6 @@ ENTITY wb_bus IS
END
wb_bus
;
ARCHITECTURE
wb_bus_arch
OF
wb_bus
IS
-- COMPONENT DECLARATIONS
COMPONENT
switch_fab_1
GENERIC
(
registered
:
IN
boolean
);
PORT
(
clk
:
IN
std_logic
;
rst
:
IN
std_logic
;
cyc_0
:
IN
std_logic
;
ack_0
:
OUT
std_logic
;
err_0
:
OUT
std_logic
;
wbo_0
:
IN
wbo_type
;
wbo_slave
:
IN
wbi_type
;
wbi_slave
:
OUT
wbo_type
;
wbi_slave_cyc
:
OUT
std_logic
);
END
COMPONENT
;
COMPONENT
switch_fab_2
GENERIC
(
registered
:
IN
boolean
);
PORT
(
clk
:
IN
std_logic
;
rst
:
IN
std_logic
;
cyc_0
:
IN
std_logic
;
ack_0
:
OUT
std_logic
;
err_0
:
OUT
std_logic
;
wbo_0
:
IN
wbo_type
;
cyc_1
:
IN
std_logic
;
ack_1
:
OUT
std_logic
;
err_1
:
OUT
std_logic
;
wbo_1
:
IN
wbo_type
;
wbo_slave
:
IN
wbi_type
;
wbi_slave
:
OUT
wbo_type
;
wbi_slave_cyc
:
OUT
std_logic
);
END
COMPONENT
;
COMPONENT
switch_fab_3
GENERIC
(
registered
:
IN
boolean
);
PORT
(
clk
:
IN
std_logic
;
rst
:
IN
std_logic
;
cyc_0
:
IN
std_logic
;
ack_0
:
OUT
std_logic
;
err_0
:
OUT
std_logic
;
wbo_0
:
IN
wbo_type
;
cyc_1
:
IN
std_logic
;
ack_1
:
OUT
std_logic
;
err_1
:
OUT
std_logic
;
wbo_1
:
IN
wbo_type
;
cyc_2
:
IN
std_logic
;
ack_2
:
OUT
std_logic
;
err_2
:
OUT
std_logic
;
wbo_2
:
IN
wbo_type
;
wbo_slave
:
IN
wbi_type
;
wbi_slave
:
OUT
wbo_type
;
wbi_slave_cyc
:
OUT
std_logic
);
END
COMPONENT
;
-- synthesis translate_off
COMPONENT
wbmon
GENERIC
(
wbname
:
string
:
=
"wbmon"
;
sets
:
std_logic_vector
(
3
DOWNTO
0
)
:
=
"1110"
;
-- 1110
-- ||||
-- |||+- write notes to Modelsim out
-- ||+-- write errors to Modelsim out
-- |+--- write notes to file out
-- +---- write errors to file out
timeout
:
integer
:
=
100
);
PORT
(
clk
:
IN
std_logic
;
rst
:
IN
std_logic
;
adr
:
IN
std_logic_vector
(
31
DOWNTO
0
);
sldat_i
:
IN
std_logic_vector
(
31
DOWNTO
0
);
sldat_o
:
IN
std_logic_vector
(
31
DOWNTO
0
);
cti
:
IN
std_logic_vector
(
2
DOWNTO
0
);
sel
:
IN
std_logic_vector
(
3
DOWNTO
0
);
cyc
:
IN
std_logic
;
stb
:
IN
std_logic
;
ack
:
IN
std_logic
;
err
:
IN
std_logic
;
we
:
IN
std_logic
);
END
COMPONENT
;
-- synthesis translate_on
-- SIGNAL DEFINITIONS
SIGNAL
wbs_0_ack
:
std_logic
;
...
...
@@ -270,7 +177,7 @@ BEGIN
wbmi_3_int
.
err
<=
wbs_4_err
(
2
);
-- sf for slave #0:
sf_0
:
switch_fab_1
sf_0
:
entity
work
.
switch_fab_1
GENERIC
MAP
(
registered
=>
FALSE
)
...
...
@@ -289,7 +196,7 @@ BEGIN
);
-- sf for slave #1:
sf_1
:
switch_fab_1
sf_1
:
entity
work
.
switch_fab_1
GENERIC
MAP
(
registered
=>
FALSE
)
...
...
@@ -308,7 +215,7 @@ BEGIN
);
-- sf for slave #2:
sf_2
:
switch_fab_2
sf_2
:
entity
work
.
switch_fab_2
GENERIC
MAP
(
registered
=>
FALSE
)
...
...
@@ -331,7 +238,7 @@ BEGIN
);
-- sf for slave #3:
sf_3
:
switch_fab_3
sf_3
:
entity
work
.
switch_fab_3
GENERIC
MAP
(
registered
=>
FALSE
)
...
...
@@ -358,7 +265,7 @@ BEGIN
);
-- sf for slave #4:
sf_4
:
switch_fab_3
sf_4
:
entity
work
.
switch_fab_3
GENERIC
MAP
(
registered
=>
FALSE
)
...
...
@@ -386,7 +293,7 @@ BEGIN
-- synthesis translate_off
wbmo_0_cyc_s
<=
'1'
WHEN
wbmo_0_cyc
=
0
ELSE
'1'
;
wbm_0
:
wbmon
wbm_0
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbm_0"
,
sets
=>
sets
,
...
...
@@ -404,11 +311,13 @@ BEGIN
stb
=>
wbmo_0
.
stb
,
ack
=>
wbmi_0_int
.
ack
,
err
=>
wbmi_0_int
.
err
,
we
=>
wbmo_0
.
we
we
=>
wbmo_0
.
we
,
er
=>
open
,
co
=>
open
);
wbmo_1_cyc_s
<=
'1'
WHEN
wbmo_1_cyc
=
0
ELSE
'1'
;
wbm_1
:
wbmon
wbm_1
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbm_1"
,
sets
=>
sets
,
...
...
@@ -426,11 +335,13 @@ BEGIN
stb
=>
wbmo_1
.
stb
,
ack
=>
wbmi_1_int
.
ack
,
err
=>
wbmi_1_int
.
err
,
we
=>
wbmo_1
.
we
we
=>
wbmo_1
.
we
,
er
=>
open
,
co
=>
open
);
wbmo_2_cyc_s
<=
'1'
WHEN
wbmo_2_cyc
=
0
ELSE
'1'
;
wbm_2
:
wbmon
wbm_2
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbm_2"
,
sets
=>
sets
,
...
...
@@ -448,11 +359,13 @@ BEGIN
stb
=>
wbmo_2
.
stb
,
ack
=>
wbmi_2_int
.
ack
,
err
=>
wbmi_2_int
.
err
,
we
=>
wbmo_2
.
we
we
=>
wbmo_2
.
we
,
er
=>
open
,
co
=>
open
);
wbmo_3_cyc_s
<=
'1'
WHEN
wbmo_3_cyc
=
'0'
ELSE
'1'
;
wbm_3
:
wbmon
wbm_3
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbm_3"
,
sets
=>
sets
,
...
...
@@ -470,10 +383,12 @@ BEGIN
stb
=>
wbmo_3
.
stb
,
ack
=>
wbmi_3_int
.
ack
,
err
=>
wbmi_3_int
.
err
,
we
=>
wbmo_3
.
we
we
=>
wbmo_3
.
we
,
er
=>
open
,
co
=>
open
);
wbs_0
:
wbmon
wbs_0
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbs_0"
,
sets
=>
sets
,
...
...
@@ -491,10 +406,12 @@ BEGIN
stb
=>
wbsi_0_int
.
stb
,
ack
=>
wbso_0
.
ack
,
err
=>
wbso_0
.
err
,
we
=>
wbsi_0_int
.
we
we
=>
wbsi_0_int
.
we
,
er
=>
open
,
co
=>
open
);
wbs_1
:
wbmon
wbs_1
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbs_1"
,
sets
=>
sets
,
...
...
@@ -512,10 +429,12 @@ BEGIN
stb
=>
wbsi_1_int
.
stb
,
ack
=>
wbso_1
.
ack
,
err
=>
wbso_1
.
err
,
we
=>
wbsi_1_int
.
we
we
=>
wbsi_1_int
.
we
,
er
=>
open
,
co
=>
open
);
wbs_2
:
wbmon
wbs_2
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbs_2"
,
sets
=>
sets
,
...
...
@@ -533,10 +452,12 @@ BEGIN
stb
=>
wbsi_2_int
.
stb
,
ack
=>
wbso_2
.
ack
,
err
=>
wbso_2
.
err
,
we
=>
wbsi_2_int
.
we
we
=>
wbsi_2_int
.
we
,
er
=>
open
,
co
=>
open
);
wbs_3
:
wbmon
wbs_3
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbs_3"
,
sets
=>
sets
,
...
...
@@ -554,10 +475,12 @@ BEGIN
stb
=>
wbsi_3_int
.
stb
,
ack
=>
wbso_3
.
ack
,
err
=>
wbso_3
.
err
,
we
=>
wbsi_3_int
.
we
we
=>
wbsi_3_int
.
we
,
er
=>
open
,
co
=>
open
);
wbs_4
:
wbmon
wbs_4
:
entity
work
.
wbmon
GENERIC
MAP
(
wbname
=>
"wbs_4"
,
sets
=>
sets
,
...
...
@@ -575,7 +498,9 @@ BEGIN
stb
=>
wbsi_4_int
.
stb
,
ack
=>
wbso_4
.
ack
,
err
=>
wbso_4
.
err
,
we
=>
wbsi_4_int
.
we
we
=>
wbsi_4_int
.
we
,
er
=>
open
,
co
=>
open
);
-- synthesis translate_on
...
...
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