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VME SBC A25 PCIe to VME bridge
Commit b6f5fc93 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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Merge branch '12-hdl-use-fifos-from-general-cores-part-1' into 'master' 

Resolve "HDL: use fifos from general cores (part 1)"

Closes #12

See merge request be-cem-edl/fec/hardware-modules/vme-sbc-a25-pcie-vme-bridge!8
parents 0897e59c 7c0d87e2
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hdl/16z091-01_src/Source/error.vhd
View file @ b6f5fc93
......@@ -44,9 +44,6 @@
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity error is
port(
clk : in std_logic;
......@@ -108,35 +105,47 @@ signal ip_error_last : std_logic_vector(14 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
err_fifo_comp : dcfifo
generic map (
intended_device_family => "Cyclone IV GX",
lpm_numwords => 4,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 2,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4)
port map (
aclr => err_fifo_clr,
-- instantiate components -----------------------------------------------------
err_fifo_comp: entity work.generic_async_fifo
generic map (
g_data_width => 16,
g_size => 8,
g_show_ahead => False,
g_with_rd_empty => True,
g_with_rd_full => False,
g_with_rd_almost_empty => False,
g_with_rd_almost_full => False,
g_with_rd_count => False,
g_with_wr_empty => False,
g_with_wr_full => False,
g_with_wr_almost_empty => False,
g_with_wr_almost_full => False,
g_with_wr_count => False,
g_almost_empty_threshold => 1,
g_almost_full_threshold => 1,
g_memory_implementation_hint => open
)
port map (
rst_n_i => err_fifo_clr,
wrclk => clk,
wrreq => err_fifo_wr_enable,
data => err_fifo_in,
wrempty => open,
wrfull => open,
clk_wr_i => clk,
d_i => err_fifo_in,
we_i => err_fifo_wr_enable,
wr_empty_o => open,
wr_full_o => open,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
rdclk => wb_clk,
rdreq => err_fifo_rd_enable,
q => err_fifo_out,
rdempty => err_fifo_empty,
rdfull => open);
clk_rd_i => wb_clk,
q_o => err_fifo_out,
rd_i => err_fifo_rd_enable,
rd_empty_o => err_fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
-------------------------------------------------------------------------------
......
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