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VME SBC A25 PCIe to VME bridge
Commit 55589ae5 authored by Tristan Gingold's avatar Tristan Gingold
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top: rework to use separate WB bus for registers 

Remove internal sram (now a dpram in the registers)
parent e30029f5
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vme-bridge @ e7a56456
Subproject commit 3f69376366bc044eeecbe6a06a7ee58f87b1e323
Subproject commit e7a564562672859b5552dcf0973ec44cb6030370
hdl/top/A25_top.vhd
View file @ 55589ae5
......@@ -184,12 +184,10 @@ END COMPONENT;
SIGNAL wbmi_0 : wbi_type;
SIGNAL wbmo_0_cyc : std_logic_vector(3 DOWNTO 0);
SIGNAL wbmo_0_cyc_bar : std_logic_vector(6 downto 0);
SIGNAL wbmo_1 : wbo_type;
SIGNAL wbmi_1 : wbi_type;
SIGNAL wbmo_1_cyc : std_logic_vector(1 DOWNTO 0);
signal wbmo_0_adr : std_logic_vector(31 downto 0);
SIGNAL wbmo_2 : wbo_type;
SIGNAL wbmi_2 : wbi_type;
SIGNAL wbmo_2_cyc : std_logic_vector(2 DOWNTO 0);
SIGNAL wbmo_2_cyc : std_logic_vector(1 DOWNTO 0);
signal wbmo_3 : wbo_type;
signal wbmo_3_cyc : std_logic;
signal wbmi_3 : wbi_type;
......@@ -212,10 +210,6 @@ END COMPONENT;
SIGNAL pll_locked : std_logic;
SIGNAL sr_d_oe : std_logic;
SIGNAL sr_d_out : std_logic_vector(15 DOWNTO 0);
SIGNAL sr_d_in : std_logic_vector(15 DOWNTO 0);
SIGNAL vme_a_out : std_logic_vector(31 downto 0);
SIGNAL vme_a_oe_n_int : std_logic;
SIGNAL vme_a_dir_int : std_logic;
......@@ -300,12 +294,9 @@ BEGIN
pll_locked_inv <= NOT pll_locked;
startup_rst <= pll_locked_inv;
wbso_3.err <= '0';
wbso_4.err <= '0';
wbmo_0.bte <= "00";
wbmo_1.bte <= "00";
wbmo_2.bte <= "00";
wbmo_1.cti <= "000";
fpga_test(1) <= 'Z';
fpga_test(2) <= 'Z';
......@@ -385,27 +376,30 @@ pll: pll_pcie
-- | 16z002-01 VME A32 | vme | 0 | 2000_0000 | 3 |
-- |16z002-01 VME CR/CSR | vme | 0 | 100_0000 | 4 |
-- +--------------------------+-----+----------+-----------+-----+
process (wbmo_0_cyc_bar, wbmo_0)
process (wbmo_0_cyc_bar, wbmo_0_adr, wbmo_0)
begin
wbmo_0_cyc <= "0000";
wbmo_0.tga(6 DOWNTO 0) <= (others => 'X');
wbmo_0.adr <= wbmo_0_adr;
if wbmo_0_cyc_bar(0) = '1' then
case wbmo_0.adr(17 DOWNTO 16) is
case wbmo_0_adr(17 DOWNTO 16) is
when "00" =>
if wbmo_0.adr(15 DOWNTO 9) = "0000000" then
if wbmo_0_adr(15 DOWNTO 9) = "0000000" then
-- Chameleon Table - cycle 0 - offset 0 - size 200 --
wbmo_0_cyc <= "0001";
elsif wbmo_0.adr(15 DOWNTO 5) = "00000010000" then
elsif wbmo_0_adr(15 DOWNTO 5) = "00000010000" then
-- 16Z126_SERFLASH - cycle 1 - offset 200 - size 20 --
wbmo_0_cyc <= "0010";
end if;
when "01" =>
wbmo_0_cyc <= "0100";
if wbmo_0.adr(8) = '1' then
if wbmo_0_adr(8) = '1' then
wbmo_0_cyc <= "0100";
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_IACK;
else
-- 16z002-01 VME regs - cycle 2 - offset 10000 - size 10000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_REGS;
wbmo_0_cyc <= "1000";
wbmo_0.adr(31 downto 10) <= (others => '0');
wbmo_0.adr(9) <= '0';
end if;
when "10" =>
-- 16z002-01 VME A16D16 - cycle 3 - offset 20000 - size 10000 --
......@@ -421,9 +415,11 @@ pll: pll_pcie
elsif wbmo_0_cyc_bar (1) = '1' then
-- 16z002-01 VME SRAM - cycle 5 - offset 0 - size 100000 --
wbmo_0_cyc <= "1000";
wbmo_0.adr(31 downto 10) <= (others => '0');
wbmo_0.adr(9) <= '1';
elsif wbmo_0_cyc_bar (2) = '1' then
wbmo_0_cyc <= "0100";
if wbmo_0.adr(24) = '0' then
if wbmo_0_adr(24) = '0' then
-- 16z002-01 VME A24D16 - cycle 6 - offset 0 - size 1000000 --
wbmo_0.tga(6 DOWNTO 0) <= CONST_VME_A24D16;
else
......@@ -442,8 +438,6 @@ pll: pll_pcie
end process;
wbmo_1.tga <= (OTHERS => '0');
wbmo_0.tga(7) <= '0'; -- indicate access from PCIE
wbmo_0.tga(8) <= '0'; -- unused
......@@ -485,7 +479,7 @@ pcie: entity work.ip_16z091_01_top
wbm_cyc_bar_o => wbmo_0_cyc_bar,
wbm_we => wbmo_0.we ,
wbm_sel => wbmo_0.sel,
wbm_adr => wbmo_0.adr,
wbm_adr => wbmo_0_adr,
wbm_dat_o => wbmo_0.dat,
wbm_cti => wbmo_0.cti,
wbm_tga => open,
......@@ -542,43 +536,9 @@ pcie: entity work.ip_16z091_01_top
dat_i => wbsi_0.dat,
dat_o => wbso_0.dat
);
srami: entity work.sram
PORT MAP (
clk66 => sys_clk,
rst => sys_rst,
stb_i => wbsi_3.stb,
ack_o => wbso_3.ack,
we_i => wbsi_3.we,
sel_i => wbsi_3.sel,
cyc_i => wbsi_3_cyc,
dat_o => wbso_3.dat,
dat_i => wbsi_3.dat,
adr_i => wbsi_3.adr(19 DOWNTO 0),
bwn => sr_bw_n,
bwan => sr_bwa_n,
bwbn => sr_bwb_n,
adscn => sr_adsc_n,
roen => sr_oe_n,
ra => sr_a,
rd_in => sr_d_in,
rd_out => sr_d_out,
rd_oe => sr_d_oe
);
sr_cs1_n <= '0'; --sys_rst; -- selected if FPGA reset is released
srdat: PROCESS(sr_d_oe, sr_d_out, sr_d)
BEGIN
IF sr_d_oe = '1' THEN
sr_d <= sr_d_out;
sr_d_in <= sr_d;
ELSE
sr_d <= (OTHERS => 'Z');
sr_d_in <= sr_d;
END IF;
END PROCESS;
sr_oe_n <= '1';
sr_cs1_n <= '1'; --sys_rst; -- selected if FPGA reset is released
sflash: entity work.z126_01_top
GENERIC MAP (
......@@ -638,7 +598,17 @@ PORT MAP (
mailbox_irq => mailbox_irq,
dma_irq => dma_irq ,
prevent_sysrst => '0',
test_vec => open,
-- Registers
wbr_stb_i => wbsi_3.stb,
wbr_cyc_i => wbsi_3_cyc,
wbr_ack_o => wbso_3.ack,
wbr_err_o => wbso_3.err,
wbr_we_i => wbsi_3.we,
wbr_sel_i => wbsi_3.sel,
wbr_adr_i => wbsi_3.adr,
wbr_dat_i => wbsi_3.dat,
wbr_dat_o => wbso_3.dat,
-- vmectrl slave
wbs_stb_i => wbsi_2.stb,
......@@ -652,18 +622,6 @@ PORT MAP (
wbs_dat_i => wbsi_2.dat,
wbs_tga_i => wbsi_2.tga,
-- vmectrl master
wbm_ctrl_stb_o => wbmo_1.stb,
wbm_ctrl_ack_i => wbmi_1.ack,
wbm_ctrl_err_i => wbmi_1.err,
wbm_ctrl_we_o => wbmo_1.we,
wbm_ctrl_sel_o => wbmo_1.sel,
wbm_ctrl_cyc_sram => wbmo_1_cyc(0),
wbm_ctrl_cyc_pci => wbmo_1_cyc(1),
wbm_ctrl_adr_o => wbmo_1.adr,
wbm_ctrl_dat_o => wbmo_1.dat,
wbm_ctrl_dat_i => wbmi_1.dat,
wbm_dma_stb_o => wbmo_2.stb,
wbm_dma_ack_i => wbmi_2.ack,
wbm_dma_we_o => wbmo_2.we,
......@@ -672,8 +630,7 @@ PORT MAP (
wbm_dma_err_i => wbmi_2.err,
wbm_dma_sel_o => wbmo_2.sel,
wbm_dma_cyc_vme => wbmo_2_cyc(0),
wbm_dma_cyc_sram => wbmo_2_cyc(1),
wbm_dma_cyc_pci => wbmo_2_cyc(2),
wbm_dma_cyc_pci => wbmo_2_cyc(1),
wbm_dma_adr_o => wbmo_2.adr,
wbm_dma_dat_o => wbmo_2.dat,
wbm_dma_dat_i => wbmi_2.dat,
......@@ -770,9 +727,6 @@ PORT MAP (
wbmo_0 => wbmo_0,
wbmi_0 => wbmi_0,
wbmo_0_cyc => wbmo_0_cyc,
wbmo_1 => wbmo_1,
wbmi_1 => wbmi_1,
wbmo_1_cyc => wbmo_1_cyc,
wbmo_2 => wbmo_2,
wbmi_2 => wbmi_2,
wbmo_2_cyc => wbmo_2_cyc,
......
hdl/top/Manifest.py
View file @ 55589ae5
......@@ -23,7 +23,6 @@ modules = {
files = [
"A25_top.vhd",
"sram.vhd",
"wb_bus.vhd",
"wb_pkg.vhd",
]
hdl/top/wb_bus.vhd
View file @ 55589ae5
......@@ -58,12 +58,9 @@ ENTITY wb_bus IS
wbmo_0 : IN wbo_type;
wbmi_0 : OUT wbi_type;
wbmo_0_cyc : IN std_logic_vector(3 DOWNTO 0);
wbmo_1 : IN wbo_type;
wbmi_1 : OUT wbi_type;
wbmo_1_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_2 : IN wbo_type;
wbmi_2 : OUT wbi_type;
wbmo_2_cyc : IN std_logic_vector(2 DOWNTO 0);
wbmo_2_cyc : IN std_logic_vector(1 DOWNTO 0);
wbmo_3 : IN wbo_type;
wbmi_3 : OUT wbi_type;
wbmo_3_cyc : IN std_logic;
......@@ -103,7 +100,9 @@ ARCHITECTURE wb_bus_arch OF wb_bus IS
SIGNAL wbs_4_ack : std_logic_vector(2 DOWNTO 0);
SIGNAL wbs_4_err : std_logic_vector(2 DOWNTO 0);
signal wbmo_1 : wbo_type;
SIGNAL wbsi_0_int : wbo_type;
SIGNAL wbsi_0_cyc_int : std_logic;
SIGNAL wbsi_1_int : wbo_type;
......@@ -116,7 +115,6 @@ ARCHITECTURE wb_bus_arch OF wb_bus IS
SIGNAL wbsi_4_cyc_int : std_logic;
SIGNAL wbmi_0_int : wbi_type;
SIGNAL wbmo_0_cyc_s : std_logic;
SIGNAL wbmi_1_int : wbi_type;
SIGNAL wbmi_2_int : wbi_type;
SIGNAL wbmo_2_cyc_s : std_logic;
SIGNAL wbmi_3_int : wbi_type;
......@@ -133,7 +131,6 @@ BEGIN
wbsi_4 <= wbsi_4_int;
wbsi_4_cyc <= wbsi_4_cyc_int;
wbmi_0 <= wbmi_0_int;
wbmi_1 <= wbmi_1_int;
wbmi_2 <= wbmi_2_int;
wbmi_3 <= wbmi_3_int;
......@@ -149,21 +146,15 @@ BEGIN
wbmi_0_int.ack <= wbs_0_ack OR wbs_1_ack OR wbs_2_ack(0) OR wbs_3_ack(0);
wbmi_0_int.err <= wbs_0_err OR wbs_1_err OR wbs_2_err(0) OR wbs_3_err(0);
-- data multiplexer for master #1
wbmi_1_int.dat <= (others => 'X');
wbmi_1_int.ack <= '0';
wbmi_1_int.err <= '0';
-- data multiplexer for master #2
data_mux (
cyc => wbmo_2_cyc,
data_in_0 => wbso_2.dat,
data_in_1 => wbso_3.dat,
data_in_2 => wbso_4.dat,
data_in_1 => wbso_4.dat,
data_out => wbmi_2_int.dat
);
wbmi_2_int.ack <= wbs_2_ack(1) OR wbs_3_ack(2) OR wbs_4_ack(1);
wbmi_2_int.err <= wbs_2_err(1) OR wbs_3_err(2) OR wbs_4_err(1);
wbmi_2_int.ack <= wbs_2_ack(1) OR wbs_4_ack(1);
wbmi_2_int.err <= wbs_2_err(1) OR wbs_4_err(1);
-- data multiplexer for master #3
wbmi_3_int.dat <= wbso_4.dat;
......@@ -232,7 +223,7 @@ BEGIN
);
-- sf for slave #3:
sf_3: entity work.switch_fab_2
sf_3: entity work.switch_fab_1
GENERIC MAP (
registered => FALSE
)
......@@ -244,10 +235,6 @@ BEGIN
cyc_0 => wbmo_0_cyc(3),
ack_0 => wbs_3_ack(0),
err_0 => wbs_3_err(0),
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(1),
ack_1 => wbs_3_ack(2),
err_1 => wbs_3_err(2),
-- slave bus:
wbo_slave => wbso_3,
wbi_slave => wbsi_3_int,
......@@ -268,7 +255,7 @@ BEGIN
ack_0 => open,
err_0 => open,
wbo_1 => wbmo_2,
cyc_1 => wbmo_2_cyc(2),
cyc_1 => wbmo_2_cyc(1),
ack_1 => wbs_4_ack(1),
err_1 => wbs_4_err(1),
wbo_2 => wbmo_3,
......
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