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VME SBC A25 PCIe to VME bridge
Commit 7d682608 authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
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ip_16z091_01: use more direct instantiations 

And remove useless component declarations
parent f5477d3a
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hdl/16z091-01_src/Source/ip_16z091_01.vhd
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hdl/16z091-01_src/Source/ip_16z091_01_top.vhd
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......@@ -296,123 +296,6 @@ signal int_ltssm : std_logic_vector(4 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component ip_16z091_01
generic(
FPGA_FAMILY : family_type := NONE;
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
READY_LATENCY : natural := 2;
FIFO_MAX_USEDW : std_logic_vector(9 downto 0) := "1111111001";
WBM_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111011";
WBM_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
WBS_SUSPEND_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111111100";
WBS_RESUME_FIFO_ACCESS : std_logic_vector(9 downto 0) := "1111110111";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000";
RX_FIFO_DEPTH : natural := 1024;
RX_LPM_WIDTHU : natural := 10;
TX_HEADER_FIFO_DEPTH : natural := 32;
TX_HEADER_LPM_WIDTHU : natural := 5;
TX_DATA_FIFO_DEPTH : natural := 1024;
TX_DATA_LPM_WIDTHU : natural := 10
);
port(
clk : in std_logic;
wb_clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
wb_rst : in std_logic;
-- IP Core
core_clk : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tl_cfg_add : in std_logic_vector(3 downto 0);
tl_cfg_ctl : in std_logic_vector(31 downto 0);
tl_cfg_ctl_wr : in std_logic;
tl_cfg_sts : in std_logic_vector(52 downto 0);
tl_cfg_sts_wr : in std_logic;
app_int_ack : in std_logic;
app_msi_ack : in std_logic;
rx_st_mask0 : out std_logic;
rx_st_ready0 : out std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
tx_st_data0 : out std_logic_vector(63 downto 0);
pme_to_cr : out std_logic;
app_int_sts : out std_logic;
app_msi_req : out std_logic;
app_msi_tc : out std_logic_vector(2 downto 0);
app_msi_num : out std_logic_vector(4 downto 0);
pex_msi_num : out std_logic_vector(4 downto 0);
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
--wbm_cyc : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0); --new
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
--wb_bar_dec : out std_logic_vector(6 downto 0);
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
wb_int : in std_logic;
wb_pwr_enable : in std_logic;
wb_int_num : in std_logic_vector(4 downto 0);
wb_int_ack : out std_logic;
wb_int_num_allowed : out std_logic_vector(5 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
rx_debug_out : out std_logic_vector(3 downto 0)
);
end component;
component hard_ip_x1
port (
-- inputs:
......@@ -735,7 +618,7 @@ begin
test_in_int(0) <= SIMULATION;
-- instanciate components
ip_16z091_01_comp : ip_16z091_01
ip_16z091_01_comp : entity work.ip_16z091_01
generic map(
FPGA_FAMILY => FPGA_FAMILY,
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES,
......
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