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VME SBC A25 PCIe to VME bridge
Commit 89a4b22a authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
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Use direct instantiations

parent 7d682608
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hdl/16z091-01_src/Source/rx_module.vhd
View file @ 89a4b22a
......@@ -107,87 +107,6 @@ architecture rx_module_arch of rx_module is
-- +----------------------------------------------------------------------------
-- NONE
-- +----------------------------------------------------------------------------
-- | components
-- +----------------------------------------------------------------------------
component rx_ctrl
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_err0 : in std_logic;
rx_st_valid0 : in std_logic;
rx_st_sop0 : in std_logic;
rx_st_eop0 : in std_logic;
rx_st_be0 : in std_logic_vector(7 downto 0);
tlp_type_i : in std_logic_vector(4 downto 0);
tlp_fmt_i : in std_logic_vector(2 downto 0);
-- FIFO
rx_fifo_c_enable_o : out std_logic;
rx_fifo_wr_enable_o : out std_logic;
-- rx_sig_manage
sop_q_i : in std_logic;
fifo_action_done_o : out std_logic;
-- rx_get_data
len_cntr_val_i : in std_logic_vector(9 downto 0)
);
end component;
component rx_get_data
port(
clk_i : in std_logic;
rst_i : in std_logic;
-- IP Core
rx_st_valid0 : in std_logic;
rx_st_data0 : in std_logic_vector(63 downto 0);
rx_st_bardec0 : in std_logic_vector(7 downto 0);
rx_st_sop0 : in std_logic;
-- FIFO
rx_fifo_in_o : out std_logic_vector(63 downto 0);
-- tx_ctrl
tag_nbr_o : out std_logic_vector(7 downto 0);
tag_rcvd_o : out std_logic;
-- rx_ctrl
len_cntr_val_o : out std_logic_vector(9 downto 0);
-- error
type_fmt_err_o : out std_logic_vector(1 downto 0);
-- rx_sig_manage
sop_q_i : in std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-- +----------------------------------------------------------------------------
-- | internal signals
-- +----------------------------------------------------------------------------
......@@ -334,7 +253,7 @@ begin
-- +----------------------------------------------------------------------------
-- | component instantiation
-- +----------------------------------------------------------------------------
rx_ctrl_comp : rx_ctrl
rx_ctrl_comp : entity work.rx_ctrl
port map(
clk_i => clk,
rst_i => rst,
......@@ -360,7 +279,7 @@ begin
len_cntr_val_i => int_len_cntr_val
);
rx_get_data_comp : rx_get_data
rx_get_data_comp : entity work.rx_get_data
port map(
clk_i => clk,
rst_i => rst,
......@@ -389,7 +308,7 @@ begin
);
c_fifo_comp : generic_dcfifo_mixedw
c_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
......@@ -410,7 +329,7 @@ begin
wrfull => int_c_wr_full,
wrusedw => int_rx_wrusedw_c);
wr_fifo_comp : generic_dcfifo_mixedw
wr_fifo_comp : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => RX_FIFO_DEPTH,
......
hdl/16z091-01_src/Source/tx_module.vhd
View file @ 89a4b22a
......@@ -157,159 +157,10 @@ signal tx_wrusedw_c : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_w : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
signal tx_wrusedw_c_out : std_logic_vector (9 downto 0);
signal tx_wrusedw_w_out : std_logic_vector (9 downto 0);
-------------------------------------------------------------------------------
-- components -----------------------------------------------------------------
component tx_ctrl
port(
clk : in std_logic;
rst : in std_logic;
-- IP core
tx_st_ready0 : in std_logic;
tx_fifo_full0 : in std_logic;
tx_fifo_empty0 : in std_logic;
tx_fifo_rdptr0 : in std_logic_vector(3 downto 0);
tx_fifo_wrptr0 : in std_logic_vector(3 downto 0);
pme_to_sr : in std_logic;
tx_st_err0 : out std_logic;
tx_st_valid0 : out std_logic;
tx_st_sop0 : out std_logic;
tx_st_eop0 : out std_logic;
pme_to_cr : out std_logic;
-- FIFO
tx_c_head_empty : in std_logic;
tx_wr_head_empty : in std_logic;
tx_c_data_empty : in std_logic;
tx_wr_data_empty : in std_logic;
tx_c_head_enable : out std_logic;
tx_wr_head_enable : out std_logic;
tx_c_data_enable : out std_logic;
tx_wr_data_enable : out std_logic;
-- tx_put_data
aligned : in std_logic;
data_len : in std_logic_vector(9 downto 0);
wr_rd : in std_logic; -- 0: write, 1: read
posted : in std_logic; -- 0: non-posted, 1: posted
byte_count : in std_logic_vector(11 downto 0);
io_write : in std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : in std_logic_vector(31 downto 0);
tx_tag_nbr : out std_logic_vector(7 downto 0);
get_header : out std_logic;
get_next_header : out std_logic;
make_header : out std_logic;
data_enable : out std_logic;
c_wrrd : out std_logic;
completer_id : out std_logic_vector(15 downto 0);
own_id : out std_logic_vector(15 downto 0);
abort_compl : out std_logic;
send_len : out std_logic_vector(9 downto 0);
send_addr : out std_logic_vector(31 downto 0);
payload_loop : out std_logic;
first_last_full : out std_logic_vector(1 downto 0);
-- tx_compl_timeout
start : out std_logic;
start_tag_nbr : out std_logic_vector(4 downto 0);
-- error
compl_abort : out std_logic;
-- init
bus_dev_func : in std_logic_vector(15 downto 0);
max_payload : in std_logic_vector(2 downto 0)
);
end component;
component tx_put_data
port(
clk : in std_logic;
rst : in std_logic;
-- IP Core
tx_st_data0 : out std_logic_vector(63 downto 0);
-- FIFO
tx_c_head_out : in std_logic_vector(63 downto 0);
tx_c_data_out : in std_logic_vector(63 downto 0);
tx_wr_head_out : in std_logic_vector(63 downto 0);
tx_wr_data_out : in std_logic_vector(63 downto 0);
-- tx_ctrl
data_enable : in std_logic;
tag_nbr : in std_logic_vector(7 downto 0);
req_id : in std_logic_vector(15 downto 0);
completer_id : in std_logic_vector(15 downto 0);
c_wrrd : in std_logic; -- 0: completion, 1: write/read
get_header : in std_logic;
get_next_header : in std_logic;
make_header : in std_logic;
abort_compl : in std_logic;
send_len : in std_logic_vector(9 downto 0); -- length of actual packet, stored to header
send_addr : in std_logic_vector(31 downto 0); -- address of actual packet, stored to header
payload_loop : in std_logic; -- =0: no loop, =1: loop -> keep most header info
first_last_full : in std_logic_vector(1 downto 0);
data_length : out std_logic_vector(9 downto 0);
aligned : out std_logic;
wr_rd : out std_logic; -- 0: write, 1: read
posted : out std_logic; -- 0: non-posted, 1: posted
byte_count : out std_logic_vector(11 downto 0);
io_write : out std_logic; -- 0: no I/O write, 1: I/O write thus completion without data
orig_addr : out std_logic_vector(31 downto 0)
);
end component;
component tx_compl_timeout
generic(
CLOCK_TIME : time := 8 ns; -- clock cycle time
TIMEOUT_TIME : integer := 25
);
port(
clk : in std_logic;
clk_500 : in std_logic; -- 500 Hz clock
rst : in std_logic;
-- tx_ctrl
tag_nbr_in : in std_logic_vector(4 downto 0);
start : in std_logic;
-- RxModule
rx_tag_nbr : in std_logic_vector(7 downto 0);
rx_tag_rcvd : in std_logic;
-- error
timeout : out std_logic
);
end component;
component generic_dcfifo_mixedw
generic (
g_device_family : string := "Cyclone IV GX";
g_fifo_depth : natural := 32;
g_data_width : natural := 32;
g_data_widthu : natural := 5;
g_q_width : natural := 64;
g_q_widthu : natural := 4;
g_showahead : string := "OFF");
port (
aclr : in std_logic := '0';
data : in std_logic_vector (g_data_width-1 downto 0);
rdclk : in std_logic ;
rdreq : in std_logic ;
wrclk : in std_logic ;
wrreq : in std_logic ;
q : out std_logic_vector (g_q_width-1 downto 0);
rdempty : out std_logic ;
wrfull : out std_logic ;
wrusedw : out std_logic_vector (g_data_widthu-1 downto 0));
end component;
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
tx_ctrl_comp : tx_ctrl
tx_ctrl_comp : entity work.tx_ctrl
port map(
clk => clk,
rst => rst,
......@@ -371,7 +222,7 @@ begin
max_payload => max_payload
);
tx_put_data_comp : tx_put_data
tx_put_data_comp : entity work.tx_put_data
port map(
clk => clk,
rst => rst,
......@@ -408,7 +259,7 @@ begin
orig_addr => orig_addr_int
);
tx_compl_timeout_comp : tx_compl_timeout
tx_compl_timeout_comp : entity work.tx_compl_timeout
generic map(
CLOCK_TIME => 8 ns, -- clock cycle time
TIMEOUT_TIME => 25
......@@ -431,7 +282,7 @@ begin
);
------------------------------------------------
tx_c_header_fifo : generic_dcfifo_mixedw
tx_c_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
......@@ -452,7 +303,7 @@ begin
wrfull => tx_fifo_c_head_full,
wrusedw => open);
tx_wr_header_fifo : generic_dcfifo_mixedw
tx_wr_header_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_HEADER_FIFO_DEPTH,
......@@ -474,7 +325,7 @@ begin
wrusedw => tx_fifo_wr_head_usedw);
------------------------------------------------
tx_c_data_fifo : generic_dcfifo_mixedw
tx_c_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
......@@ -495,7 +346,7 @@ begin
wrfull => tx_fifo_c_data_full,
wrusedw => tx_wrusedw_c);
tx_w_data_fifo : generic_dcfifo_mixedw
tx_w_data_fifo : entity work.generic_dcfifo_mixedw
generic map (
g_device_family => DEVICE_FAMILY,
g_fifo_depth => TX_DATA_FIFO_DEPTH,
......
hdl/16z091-01_src/Source/z091_01_wb_master.vhd
View file @ 89a4b22a
......@@ -101,20 +101,6 @@ end entity z091_01_wb_master;
-- ****************************************************************************
architecture z091_01_wb_master_arch of z091_01_wb_master is
component z091_01_wb_adr_dec
generic(
NR_OF_WB_SLAVES : integer range 63 downto 1 := 1
);
port (
pci_cyc_i : in std_logic_vector(6 downto 0);
wbm_adr_o_q : in std_logic_vector(31 downto 2);
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES -1 downto 0)
);
end component;
-- FSM state encoding ---------------------------------------------------------
type fsm_state is (
PREPARE_FIFO, IDLE, GET_HEADER_0, GET_HEADER_1, GET_HEADER_2, GET_WR_DATA, START_TRANS,
......@@ -170,7 +156,7 @@ signal wbm_cyc_o_int : std_logic_vector(NR_OF_WB_SLAVES -1 downto 0);
begin
z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
z091_01_wb_adr_dec_comp : entity work.z091_01_wb_adr_dec
generic map(
NR_OF_WB_SLAVES => NR_OF_WB_SLAVES
)
......
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