16z091-01_src: simplify tx_module.vhd

a00c53bd · Tristan Gingold · 27402512 · a00c53bd
Commit a00c53bd authored Jan 16, 2024 by Tristan Gingold
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tx_module.vhd hdl/16z091-01_src/Source/tx_module.vhd +2 -6

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--- a/hdl/16z091-01_src/Source/tx_module.vhd
+++ b/hdl/16z091-01_src/Source/tx_module.vhd
@@ -155,8 +155,6 @@ signal tx_fifo_w_data_out_int     : std_logic_vector(63 downto 0);

 signal tx_wrusedw_c     : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
 signal tx_wrusedw_w     : std_logic_vector (TX_DATA_LPM_WIDTHU-1 downto 0);
-signal tx_wrusedw_c_out : std_logic_vector (9 downto 0);
-signal tx_wrusedw_w_out : std_logic_vector (9 downto 0);

 begin
 -- instanciate components -----------------------------------------------------
@@ -367,9 +365,7 @@ begin
      wrfull  => tx_fifo_w_data_full,
      wrusedw => tx_wrusedw_w);
 -------------------------------------------------------------------------------
-   tx_wrusedw_c_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_c),10);
-   tx_wrusedw_w_out <= conv_std_logic_vector(conv_integer(tx_wrusedw_w),10);
-   tx_fifo_c_data_usedw <= tx_wrusedw_c_out;
-   tx_fifo_w_data_usedw <= tx_wrusedw_w_out;
+   tx_fifo_c_data_usedw <= "000" & tx_wrusedw_c(6 downto 0);
+   tx_fifo_w_data_usedw <= "000" & tx_wrusedw_w(6 downto 0);
 -------------------------------------------------------------------------------
 end architecture tx_module_arch;