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VME SBC A25 PCIe to VME bridge
Commit ddc8ce18 authored by Tristan Gingold's avatar Tristan Gingold Committed by Tristan Gingold
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A25_top: remove configurations, remove a component

parent 9c977984
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hdl/top/A25_top.vhd
View file @ ddc8ce18
......@@ -124,101 +124,6 @@ END A25_top;
ARCHITECTURE A25_top_arch OF A25_top IS
CONSTANT NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 10;
COMPONENT ip_16z091_01_top
GENERIC(
SIMULATION : std_logic := '0'; -- =1 simulation,=0 synthesis
FPGA_FAMILY : family_type := NONE;
IRQ_WIDTH : integer range 32 downto 1 := 1;
-- only use one of the following 3:
-- 001 := 1 lane, 010 := 2 lanes, 100 := 4 lanes
USE_LANES : std_logic_vector(2 downto 0) := "001";
NR_OF_WB_SLAVES : natural range 63 DOWNTO 1 := 12;
NR_OF_BARS_USED : natural range 6 downto 1 := 5;
VENDOR_ID : natural := 16#1A88#;
DEVICE_ID : natural := 16#4D45#;
REVISION_ID : natural := 16#0#;
CLASS_CODE : natural := 16#068000#;
SUBSYSTEM_VENDOR_ID : natural := 16#9B#;
SUBSYSTEM_DEVICE_ID : natural := 16#5A91#;
BAR_MASK_0 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_1 : std_logic_vector(31 downto 0) := x"FF000008";
BAR_MASK_2 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_3 : std_logic_vector(31 downto 0) := x"FF000000";
BAR_MASK_4 : std_logic_vector(31 downto 0) := x"FF000001";
BAR_MASK_5 : std_logic_vector(31 downto 0) := x"FF000001";
PCIE_REQUEST_LENGTH : std_logic_vector(9 downto 0) := "0000100000"; -- 32DW = 128Byte
RX_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10;
TX_HEADER_LPM_WIDTHU : integer range 10 DOWNTO 5 := 5;
TX_DATA_LPM_WIDTHU : integer range 10 DOWNTO 5 := 10
);
PORT(
-- Hard IP ports:
clk_50 : in std_logic; -- 50 MHz clock for reconfig_clk and cal_blk_clk
clk_125 : in std_logic; -- 125 MHz clock for fixed_clk
ref_clk : in std_logic; -- 100 MHz reference clock
clk_500 : in std_logic; -- 500 Hz clock
ext_rst_n : in std_logic;
rx_0 : in std_logic;
rx_1 : in std_logic;
rx_2 : in std_logic;
rx_3 : in std_logic;
tx_0 : out std_logic;
tx_1 : out std_logic;
tx_2 : out std_logic;
tx_3 : out std_logic;
-- Wishbone ports:
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Wishbone master
wbm_ack : in std_logic;
wbm_dat_i : in std_logic_vector(31 downto 0);
wbm_stb : out std_logic;
wbm_cyc_o : out std_logic_vector(NR_OF_WB_SLAVES - 1 downto 0);
wbm_we : out std_logic;
wbm_sel : out std_logic_vector(3 downto 0);
wbm_adr : out std_logic_vector(31 downto 0);
wbm_dat_o : out std_logic_vector(31 downto 0);
wbm_cti : out std_logic_vector(2 downto 0);
wbm_tga : out std_logic;
-- Wishbone slave
wbs_cyc : in std_logic;
wbs_stb : in std_logic;
wbs_we : in std_logic;
wbs_sel : in std_logic_vector(3 downto 0);
wbs_adr : in std_logic_vector(31 downto 0);
wbs_dat_i : in std_logic_vector(31 downto 0);
wbs_cti : in std_logic_vector(2 downto 0);
wbs_tga : in std_logic; -- 0: memory, 1: I/O
wbs_ack : out std_logic;
wbs_err : out std_logic;
wbs_dat_o : out std_logic_vector(31 downto 0);
-- interrupt
irq_req_i : in std_logic_vector(IRQ_WIDTH -1 downto 0);
-- error
error_timeout : out std_logic;
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- debug port
link_train_active : out std_logic
);
END COMPONENT;
COMPONENT pll_pcie
PORT
......@@ -488,7 +393,7 @@ pll: pll_pcie
CONST_VME_CRCSR WHEN wbmo_0_cyc_int(9) = '1' ELSE -- |16z002-01 VME CRCSR | 9 | 0 | 1000000 | 4 |
(OTHERS => '0'); -- +--------------------------+-----+----------+----------+-----+
pcie: ip_16z091_01_top
pcie: entity work.ip_16z091_01_top
GENERIC MAP (
SIMULATION => f_sel_sim_bool(SIMULATION),
FPGA_FAMILY => CYCLONE4,
......@@ -578,7 +483,8 @@ pcie: ip_16z091_01_top
error_r2c0 => open,
error_msi_num => open,
link_train_active => open
link_train_active => open,
gp_debug_port => open
);
......@@ -843,74 +749,3 @@ PORT MAP (
-------------------------------------------------------------------------------------------------------------
END A25_top_arch;
-- CONFIGURATION wbm_cfg OF pcies_wbm_ctrl IS
-- FOR pcies_wbm_ctrl_arch
-- FOR wb_adr_dec_inst : pcies_wb_adr_dec
-- USE ENTITY work.pcies_wb_adr_dec(wb_adr_dec_arch);
-- END FOR;
-- END FOR;
-- END CONFIGURATION wbm_cfg;
--
-- CONFIGURATION pcies_wbm_cfg OF pcies_wbm IS
-- FOR pcies_wbm_arch
-- FOR wbm : pcies_wbm_ctrl
-- USE CONFIGURATION work.wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies_wbm_cfg;
--
-- CONFIGURATION pcies2wbb_cfg OF pcies2wbb_top IS
-- FOR pcies2wbb_top_arch
-- FOR pcies_wbm_i : pcies_wbm
-- USE CONFIGURATION work.pcies_wbm_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION pcies2wbb_cfg;
--
-- CONFIGURATION top_cfg of A25_top IS
-- FOR A25_top_arch
-- FOR pcie : pcies2wbb_top
-- USE CONFIGURATION work.pcies2wbb_cfg;
-- END FOR;
-- END FOR;
-- END CONFIGURATION top_cfg;
-- Configurations for 16z091-01 address decoder
CONFIGURATION z091_01_wb_master_cfg OF z091_01_wb_master IS
FOR z091_01_wb_master_arch
FOR z091_01_wb_adr_dec_comp : z091_01_wb_adr_dec
USE ENTITY work.z091_01_wb_adr_dec(a25_arch);
END FOR;
END FOR;
END CONFIGURATION z091_01_wb_master_cfg;
CONFIGURATION ip_16z091_01_cfg OF ip_16z091_01 IS
FOR ip_16z091_01_arch
FOR wb_master_comp : z091_01_wb_master
USE CONFIGURATION work.z091_01_wb_master_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_cfg;
CONFIGURATION ip_16z091_01_top_cfg OF ip_16z091_01_top IS
FOR ip_16z091_01_top_arch
FOR ip_16z091_01_comp : ip_16z091_01
USE CONFIGURATION work.ip_16z091_01_cfg;
END FOR;
END FOR;
END CONFIGURATION ip_16z091_01_top_cfg;
CONFIGURATION top_cfg OF A25_top IS
FOR A25_top_arch
FOR pcie : ip_16z091_01_top
USE CONFIGURATION work.ip_16z091_01_top_cfg;
END FOR;
for srami: sram
use entity work.sram(internal);
end for;
END FOR;
END CONFIGURATION top_cfg;
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