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VME64x core
Commits
01b08fee
Commit
01b08fee
authored
Sep 20, 2017
by
Tristan Gingold
Browse files
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xvme64x_core component: remove unused generics.
parent
16982f5f
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1 changed file
with
1 addition
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25 deletions
+1
-25
xvme64x_core_pkg.vhd
hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+1
-25
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hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
View file @
01b08fee
...
@@ -97,35 +97,27 @@ package xvme64x_core_pkg is
...
@@ -97,35 +97,27 @@ package xvme64x_core_pkg is
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_END_SN
:
std_logic_vector
(
23
downto
0
)
:
=
x"000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"ff000000"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_0000bb00"
;
g_F0_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F0_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"fff80000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F1_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"bb000000_00000000"
;
g_F1_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F1_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F2_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F2_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F3_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F3_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F4_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F4_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F5_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F5_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F6_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F6_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_ADEM
:
std_logic_vector
(
31
downto
0
)
:
=
x"00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_AMCAP
:
std_logic_vector
(
63
downto
0
)
:
=
x"00000000_00000000"
;
g_F7_XAMCAP
:
std_logic_vector
(
255
downto
0
)
:
=
x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000"
;
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
g_F7_DAWPR
:
std_logic_vector
(
7
downto
0
)
:
=
x"84"
);
);
port
(
port
(
...
@@ -170,23 +162,7 @@ package xvme64x_core_pkg is
...
@@ -170,23 +162,7 @@ package xvme64x_core_pkg is
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
user_csr_data_o
:
out
std_logic_vector
(
7
downto
0
);
user_csr_we_o
:
out
std_logic
;
user_csr_we_o
:
out
std_logic
;
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
)
f0_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f0_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f3_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f4_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f5_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f6_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f7_dfs_adem_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
)
);
);
end
component
xvme64x_core
;
end
component
xvme64x_core
;
...
...
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