Commit 20629818 authored by Mathieu Saccani's avatar Mathieu Saccani

Add some missing reset values, so the signals propagated to the WB are not 'X'…

Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts.
parent f50d79fc
......@@ -342,20 +342,32 @@ begin
-- WB
s_wb_start <= '0';
vme_cycles <= (others => '0');
vme_idff_addr <= (others => '0');
vme_idff_data <= (others => '0');
vme_idff_am <= (others => '0');
vme_idff_ds_n <= (others => '1');
vme_idff_write_n <= '1';
vme_idff_lword_n <= '0';
vme_odff_addr <= (others => '0');
vme_odff_data <= (others => '0');
load_addr_reg_phase1 <= '0';
load_addr_reg_phase2 <= '0';
s_transferType <= TFR_ERROR;
s_2e_dtack <= '0';
s_DS_latch_count <= (others => '0');
s_setup <= (others => '0');
s_sst_timing <= (others => '0');
s_card_sel <= '0';
s_conf_sel <= '0';
s_irq_sel <= '0';
irq_ack_o <= '0';
else
s_conf_req <= '0';
decode_start_o <= '0';
......@@ -931,9 +943,18 @@ begin
addr_reg <= (others => '0');
lword_n_reg <= '0';
data_reg <= (others => '0');
s_err <= '0';
s_wb_done <= '0';
s_cross_boundary <= '0';
inc_reg <= (others => '0');
s_stall <= '0';
s_wb_dataphase <= '0';
else
case s_WBFSMstate is
when IDLE =>
......
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