Add some missing reset values, so the signals propagated to the WB are not 'X'…

Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts.

Add some missing reset values, so the signals propagated to the WB are not 'X'…
Add some missing reset values, so the signals propagated to the WB are not 'X' when the simulation starts.
20629818 · Mathieu Saccani · f50d79fc · 20629818
Commit 20629818 authored Oct 19, 2023 by Mathieu Saccani
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Showing with 55 additions and 34 deletions

vme_bus.vhd hdl/rtl/vme_bus.vhd +55 -34

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--- a/hdl/rtl/vme_bus.vhd
+++ b/hdl/rtl/vme_bus.vhd
@@ -322,55 +322,67 @@ begin
        -- FSM reset after power up,
        -- software reset, manually reset,
        -- on rising edge of AS.
-        s_conf_req       <= '0';
-        decode_start_o   <= '0';
+        s_conf_req           <= '0';
+        decode_start_o       <= '0';

        -- VME
-        vme_odff_dtack_oe <= '0';
-        vme_odff_dtack_n  <= '1';
+        vme_odff_dtack_oe    <= '0';
+        vme_odff_dtack_n     <= '1';
        vme_dtack_async_ctrl <= '0';
-        vme_odff_retry_oe <= '0';
-        vme_odff_retry_n <= '1';
-        vme_odff_data_dir <= '0';
-        vme_odff_addr_dir <= '0';
-        vme_odff_lword_n  <= '0';
-        vme_berr_n_o      <= '1';
-        vme_iackout_n_o   <= '1';
-        s_MBLT_Data       <= '0';
-        s_mainFSMstate    <= IDLE;
+        vme_odff_retry_oe    <= '0';
+        vme_odff_retry_n     <= '1';
+        vme_odff_data_dir    <= '0';
+        vme_odff_addr_dir    <= '0';
+        vme_odff_lword_n     <= '0';
+        vme_berr_n_o         <= '1';
+        vme_iackout_n_o      <= '1';
+        s_MBLT_Data          <= '0';
+        s_mainFSMstate       <= IDLE;

        -- WB
-        s_wb_start	 <= '0';
+        s_wb_start	         <= '0';

-        vme_idff_addr    <= (others => '0');
-        vme_idff_am      <= (others => '0');
+        vme_cycles           <= (others => '0');
+        vme_idff_addr        <= (others => '0');
+        vme_idff_data        <= (others => '0');
+        vme_idff_am          <= (others => '0');
+        vme_idff_ds_n        <= (others => '1');
+        vme_idff_write_n     <= '1';
+        vme_idff_lword_n     <= '0';

-        vme_odff_addr   <= (others => '0');
+        vme_odff_addr        <= (others => '0');
+        vme_odff_data        <= (others => '0');

        load_addr_reg_phase1 <= '0';
        load_addr_reg_phase2 <= '0';

-        s_transferType <= TFR_ERROR;
-
-        s_card_sel <= '0';
-        s_conf_sel <= '0';
-        s_irq_sel  <= '0';
-        irq_ack_o  <= '0';
+        s_transferType       <= TFR_ERROR;
+        
+        s_2e_dtack           <= '0';
+        s_DS_latch_count     <= (others => '0');
+        s_setup              <= (others => '0');
+        s_sst_timing         <= (others => '0');
+
+        s_card_sel           <= '0';
+        s_conf_sel           <= '0';
+        s_irq_sel            <= '0';
+        irq_ack_o            <= '0';
+        
      else
-        s_conf_req       <= '0';
-        decode_start_o   <= '0';
-        vme_odff_dtack_oe <= '0';
-        vme_odff_dtack_n <= '1';
-        vme_odff_retry_oe <= '0';
-        vme_odff_retry_n <= '1';
+        s_conf_req           <= '0';
+        decode_start_o       <= '0';
+        vme_odff_dtack_oe    <= '0';
+        vme_odff_dtack_n     <= '1';
+        vme_odff_retry_oe    <= '0';
+        vme_odff_retry_n     <= '1';
        vme_dtack_async_ctrl <= '0';
-        vme_berr_n_o     <= '1';
-        vme_iackout_n_o  <= '1';
-        irq_ack_o        <= '0';
+        vme_berr_n_o         <= '1';
+        vme_iackout_n_o      <= '1';
+        irq_ack_o            <= '0';

        load_addr_reg_phase1 <= '0';
        load_addr_reg_phase2 <= '0';
-        s_wb_start	 <= '0';
+        s_wb_start	         <= '0';

        case s_mainFSMstate is

@@ -930,10 +942,19 @@ begin
        wb_we_o          <= '0';
        addr_reg         <= (others => '0');
        lword_n_reg      <= '0';
+        
+        data_reg         <= (others => '0');

        s_err            <= '0';
-        s_wb_done		     <= '0';
+        s_wb_done		 <= '0';
        s_cross_boundary <= '0';
+        
+        inc_reg          <= (others => '0');
+        
+        s_stall          <= '0'; 
+        
+        s_wb_dataphase   <= '0';
+        
      else
        case s_WBFSMstate is
          when IDLE =>