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VME64x core
Commit 2460adc3 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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serial bridge: initial working version

parent 6f359655
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Showing with 609 additions and 332 deletions
hdl/rtl/Manifest.py
View file @ 2460adc3
files = [ "vme64x_core.vhd", files = ["serial_bridge_master.vhd",
"xvme64x_core_master.vhd", "serial_bridge_slave.vhd",
"xvme64x_core_slave.vhd", "vme64x_core.vhd",
"vme64x_pkg.vhd", "vme64x_pkg.vhd",
"vme_bus.vhd", "vme_bus_bridge.vhd",
"vme_bus_bridge.vhd", "vme_bus.vhd",
"vme_cr_csr_space.vhd", "vme_cr_csr_space.vhd",
"vme_funct_match.vhd", "vme_funct_match.vhd",
"vme_irq_controller.vhd", "vme_irq_controller.vhd",
"vme_user_csr.vhd", "vme_user_csr.vhd",
"bridge_master.vhd", "xvme64x_bridge_serdes.vhd",
"bridge_slave.vhd" "xvme64x_core_master.vhd",
"xvme64x_core_slave.vhd",
# "xvme64x_core.vhd" "xvme64x_core.vhd"];
]
hdl/rtl/bridge_master.vhd → hdl/rtl/serial_bridge_master.vhd
View file @ 2460adc3
...@@ -8,7 +8,7 @@ use work.vme64x_pkg.all; ...@@ -8,7 +8,7 @@ use work.vme64x_pkg.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity bridge_master is entity serial_bridge_master is
generic( generic(
g_clock_period : integer g_clock_period : integer
); );
...@@ -17,9 +17,9 @@ entity bridge_master is ...@@ -17,9 +17,9 @@ entity bridge_master is
afpga_rst_n_i : in std_logic; afpga_rst_n_i : in std_logic;
afpga_clk_i : in std_logic; afpga_clk_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0); afpga_d_i : in std_logic_vector(15 downto 0);
afpga_frame_i : in std_logic; afpga_frame_i : in std_logic;
afpga_d_o : out std_logic_vector(7 downto 0); afpga_d_o : out std_logic_vector(15 downto 0);
afpga_frame_o : out std_logic; afpga_frame_o : out std_logic;
vme_berr_n_i : in std_logic; vme_berr_n_i : in std_logic;
...@@ -63,9 +63,9 @@ entity bridge_master is ...@@ -63,9 +63,9 @@ entity bridge_master is
irq_ack_i : in std_logic irq_ack_i : in std_logic
); );
end bridge_master; end serial_bridge_master;
architecture rtl of bridge_master is architecture rtl of serial_bridge_master is
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0"; constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1"; constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
...@@ -82,7 +82,6 @@ architecture rtl of bridge_master is ...@@ -82,7 +82,6 @@ architecture rtl of bridge_master is
signal afpga_din : std_logic_vector(15 downto 0); signal afpga_din : std_logic_vector(15 downto 0);
signal afpga_frame_out : std_logic; signal afpga_frame_out : std_logic;
signal afpga_frame_in : std_logic; signal afpga_frame_in : std_logic;
signal afpga_clk_n : std_logic;
signal mem_ack_int : std_logic; signal mem_ack_int : std_logic;
...@@ -123,65 +122,12 @@ architecture rtl of bridge_master is ...@@ -123,65 +122,12 @@ architecture rtl of bridge_master is
begin begin
mem_ack_o <= mem_ack_int; mem_ack_o <= mem_ack_int;
afpga_clk_n <= not afpga_clk_i;
gen_ddr_ios : for i in 0 to 7 generate
U_ODDR_Data : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_d_o(i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_dout(2*i),
D1 => afpga_dout(2*i+1),
R => '0',
S => '0');
U_IDDR_Data : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => afpga_din(2*i+1),
Q1 => afpga_din(2*i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_d_i(i),
R => '0',
S => '0');
end generate gen_ddr_ios;
U_IDDR_Frame : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => afpga_frame_in,
Q1 => open,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_frame_i,
R => '0',
S => '0');
U_ODDR_Frame : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_frame_o,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_frame_out,
D1 => afpga_frame_out,
R => '0',
S => '0');
afpga_d_o <= afpga_dout;
afpga_frame_o <= afpga_frame_out;
afpga_frame_in <= afpga_frame_i;
afpga_din <= afpga_d_i;
p_in_fsm : process(afpga_clk_i) p_in_fsm : process(afpga_clk_i)
begin begin
......
hdl/rtl/bridge_slave.vhd → hdl/rtl/serial_bridge_slave.vhd
View file @ 2460adc3
...@@ -34,7 +34,7 @@ use work.wishbone_pkg.all; ...@@ -34,7 +34,7 @@ use work.wishbone_pkg.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity bridge_slave is entity serial_bridge_slave is
generic ( generic (
g_CLOCK_PERIOD : integer g_CLOCK_PERIOD : integer
); );
...@@ -43,9 +43,9 @@ entity bridge_slave is ...@@ -43,9 +43,9 @@ entity bridge_slave is
sfpga_rst_n_i : in std_logic; sfpga_rst_n_i : in std_logic;
sfpga_clk_i : in std_logic; sfpga_clk_i : in std_logic;
sfpga_d_i : in std_logic_vector(7 downto 0); sfpga_d_i : in std_logic_vector(15 downto 0);
sfpga_frame_i : in std_logic; sfpga_frame_i : in std_logic;
sfpga_d_o : out std_logic_vector(7 downto 0); sfpga_d_o : out std_logic_vector(15 downto 0);
sfpga_frame_o : out std_logic; sfpga_frame_o : out std_logic;
vme_aux_valid_o : out std_logic; vme_aux_valid_o : out std_logic;
...@@ -93,9 +93,9 @@ entity bridge_slave is ...@@ -93,9 +93,9 @@ entity bridge_slave is
irq_pending_i : in std_logic; irq_pending_i : in std_logic;
irq_ack_o : out std_logic irq_ack_o : out std_logic
); );
end bridge_slave; end serial_bridge_slave;
architecture rtl of bridge_slave is architecture rtl of serial_bridge_slave is
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0"; constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1"; constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
...@@ -116,6 +116,8 @@ architecture rtl of bridge_slave is ...@@ -116,6 +116,8 @@ architecture rtl of bridge_slave is
signal cr_csr_write : std_logic; signal cr_csr_write : std_logic;
signal addr_decoder_reg : std_logic_vector(31 downto 1);
type t_rx_state is type t_rx_state is
( (
IDLE, IDLE,
...@@ -148,86 +150,12 @@ architecture rtl of bridge_slave is ...@@ -148,86 +150,12 @@ architecture rtl of bridge_slave is
begin begin
sfpga_clk_n <= not sfpga_clk_i;
gen_ddr_ios : for i in 0 to 7 generate
U_ODDR_Data : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => sfpga_d_o(i),
C0 => sfpga_clk_i,
C1 => sfpga_clk_n,
CE => '1',
D0 => sfpga_dout(2*i),
D1 => sfpga_dout(2*i+1),
R => '0',
S => '0');
U_IDDR_Data : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => sfpga_din(2*i+1),
Q1 => sfpga_din(2*i),
C0 => sfpga_clk_i,
C1 => sfpga_clk_n,
CE => '1',
D => sfpga_d_i(i),
R => '0',
S => '0');
end generate gen_ddr_ios;
U_IDDR_Frame : IDDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q0 => sfpga_frame_in,
Q1 => open,
C0 => sfpga_clk_i,
C1 => sfpga_clk_n,
CE => '1',
D => sfpga_frame_i,
R => '0',
S => '0');
U_ODDR_Frame : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => sfpga_frame_o,
C0 => sfpga_clk_i,
C1 => sfpga_clk_n,
CE => '1',
D0 => sfpga_frame_out,
D1 => sfpga_frame_out,
R => '0',
S => '0');
-- if decode_start_i = '1' then
-- afpga_frame_out <= '1';
-- afpga_dout <= c_tag_decode_req & am_i & "000000";
-- tx_state <= TX_DECODE_REQ0;
-- end if;
-- when TX_CSR_REQ =>
-- afpga_frame_out <= '0';
-- afpga_dout <= cr_csr_addr_i(4 downto 0) & "000" & cr_csr_data_i;
-- tx_state <= RX_CSR_ACK;
-- when RX_CSR_ACK =>
-- if afpga_frame_in = '1' and afpga_din(15 downto 12) = c_tag_csr_rsp then
-- cr_csr_done_o <= '1';
-- cr_csr_data_o <= afpga_din(7 downto 0);
-- tx_state <= IDLE;
-- end if;
sfpga_frame_in <= sfpga_frame_i;
sfpga_din <= sfpga_d_i;
sfpga_frame_o <= sfpga_frame_out;
sfpga_d_o <= sfpga_dout;
p_in_fsm : process(sfpga_clk_i) p_in_fsm : process(sfpga_clk_i)
variable send_cfg : boolean := false; variable send_cfg : boolean := false;
...@@ -242,6 +170,9 @@ begin ...@@ -242,6 +170,9 @@ begin
cr_csr_we_o <= '0'; cr_csr_we_o <= '0';
mem_req_o <= '0'; mem_req_o <= '0';
sfpga_dout <= (others => '0');
sfpga_frame_out <= '0';
else else
-- report "Din " & integer'image(to_integer(unsigned(sfpga_din))); -- report "Din " & integer'image(to_integer(unsigned(sfpga_din)));
...@@ -409,16 +340,17 @@ begin ...@@ -409,16 +340,17 @@ begin
sfpga_dout(15 downto 12) <= c_tag_decode_rsp; sfpga_dout(15 downto 12) <= c_tag_decode_rsp;
sfpga_dout(11) <= decode_sel_i; sfpga_dout(11) <= decode_sel_i;
rx_state <= TX_DECODE_RSP1; rx_state <= TX_DECODE_RSP1;
addr_decoder_reg <= addr_decoder_i;
end if; end if;
when TX_DECODE_RSP1 => when TX_DECODE_RSP1 =>
sfpga_frame_out <= '0'; sfpga_frame_out <= '0';
sfpga_dout <= addr_decoder_i(31 downto 16); sfpga_dout <= addr_decoder_reg(31 downto 16);
rx_state <= TX_DECODE_RSP2; rx_state <= TX_DECODE_RSP2;
when TX_DECODE_RSP2 => when TX_DECODE_RSP2 =>
sfpga_frame_out <= '0'; sfpga_frame_out <= '0';
sfpga_dout(15 downto 1) <= addr_decoder_i(15 downto 1); sfpga_dout(15 downto 1) <= addr_decoder_reg(15 downto 1);
rx_state <= IDLE; rx_state <= IDLE;
......
hdl/rtl/vme64x_pkg.vhd
View file @ 2460adc3
...@@ -43,6 +43,8 @@ package vme64x_pkg is ...@@ -43,6 +43,8 @@ package vme64x_pkg is
-- Constants -- Constants
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
type t_BRIDGE_SERDES_MODE is ( MASTER, SLAVE );
-- Manufactuer IDs. -- Manufactuer IDs.
constant c_CERN_ID : std_logic_vector(23 downto 0) := x"080030"; constant c_CERN_ID : std_logic_vector(23 downto 0) := x"080030";
......
hdl/rtl/vme_bus.vhd
View file @ 2460adc3
...@@ -34,46 +34,36 @@ use work.wishbone_pkg.all; ...@@ -34,46 +34,36 @@ use work.wishbone_pkg.all;
entity vme_bus is entity vme_bus is
generic ( generic (
g_CLOCK_PERIOD : integer; g_CLOCK_PERIOD : integer;
g_BRIDGED_MODE : boolean; g_WB_GRANULARITY : t_wishbone_address_granularity;
g_WB_GRANULARITY : t_wishbone_address_granularity g_WB_MODE : t_wishbone_interface_mode
); );
port ( port (
clk_i : in std_logic; clk_i : in std_logic;
rst_n_i : in std_logic; rst_n_i : in std_logic;
-- Bridge signals -- VME signals
vme_as_n_i : in std_logic;
bridge_addr_req_i : in std_logic; vme_lword_n_o : out std_logic := '0';
bridge_addr_i : in std_logic_vector(31 downto 1); vme_lword_n_i : in std_logic;
bridge_addr_am_i : in std_logic_vector(5 downto 0); vme_retry_n_o : out std_logic;
bridge_addr_lword_n_i : in std_logic; vme_retry_oe_o : out std_logic;
vme_write_n_i : in std_logic;
bridge_write_req_i : in std_logic; vme_ds_n_i : in std_logic_vector(1 downto 0);
bridge_write_ack_o : out std_logic; vme_dtack_n_o : out std_logic;
bridge_write_ds_n_i : in std_logic_vector(1 downto 0); vme_dtack_oe_o : out std_logic;
bridge_write_data_i : in std_logic_vector(63 downto 0); vme_berr_n_o : out std_logic;
bridge_write_write_n_i : in std_logic; vme_addr_i : in std_logic_vector(31 downto 1);
vme_addr_o : out std_logic_vector(31 downto 1) := (others => '0');
bridge_read_req_i : in std_logic; vme_addr_dir_o : out std_logic;
bridge_read_ack_o : out std_logic; vme_addr_oe_n_o : out std_logic;
bridge_read_ds_n_i : in std_logic_vector(1 downto 0); vme_data_i : in std_logic_vector(31 downto 0);
bridge_read_write_n_i: in std_logic; vme_data_o : out std_logic_vector(31 downto 0) := (others => '0');
vme_data_dir_o : out std_logic;
bridge_cpl_req_o : out std_logic; vme_data_oe_n_o : out std_logic;
bridge_cpl_ack_i : in std_logic; vme_am_i : in std_logic_vector(5 downto 0);
bridge_cpl_data_o : out std_logic_vector(63 downto 0); vme_iackin_n_i : in std_logic;
bridge_cpl_has_data_o : out std_logic; vme_iack_n_i : in std_logic;
bridge_cpl_dtack_n_o : out std_logic; vme_iackout_n_o : out std_logic;
bridge_cpl_berr_o : out std_logic;
bridge_cpl_addr_dir_o : out std_logic;
bridge_cpl_data_dir_o : out std_logic;
bridge_aux_valid_i : in std_logic;
bridge_aux_iack_n_i : in std_logic;
bridge_aux_iackin_n_i : in std_logic;
bridge_aux_iackout_n_o : out std_logic;
bridge_aux_irq_n_o : out std_logic_vector(7 downto 1);
-- WB signals -- WB signals
wb_stb_o : out std_logic; wb_stb_o : out std_logic;
...@@ -163,6 +153,8 @@ architecture rtl of vme_bus is ...@@ -163,6 +153,8 @@ architecture rtl of vme_bus is
-- Decoding ADDR and AM (selecting card or conf). -- Decoding ADDR and AM (selecting card or conf).
DECODE_ACCESS, DECODE_ACCESS,
-- Wait until DS is asserted.
WAIT_FOR_DS,
-- Wait until DS is stable (and asserted). -- Wait until DS is stable (and asserted).
LATCH_DS, LATCH_DS,
...@@ -189,8 +181,10 @@ architecture rtl of vme_bus is ...@@ -189,8 +181,10 @@ architecture rtl of vme_bus is
IRQ_CHECK, IRQ_CHECK,
-- Pass IACKIN to IACKOUT -- Pass IACKIN to IACKOUT
IRQ_PASS IRQ_PASS,
-- Wait until AS is deasserted
WAIT_END
); );
-- Main FSM signals -- Main FSM signals
...@@ -206,6 +200,9 @@ architecture rtl of vme_bus is ...@@ -206,6 +200,9 @@ architecture rtl of vme_bus is
signal s_err : std_logic; signal s_err : std_logic;
-- Stall status. Set to one until wb_stall_i is cleared.
signal s_stall : std_logic;
-- Calculate the number of LATCH DS states necessary to match the timing -- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987. -- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
-- (max skew for the slave is 20 ns) -- (max skew for the slave is 20 ns)
...@@ -222,6 +219,8 @@ begin ...@@ -222,6 +219,8 @@ begin
-- L | L | B to A L | L | B to Y -- L | L | B to A L | L | B to Y
-- H | L |A to B, B to Y | -- H | L |A to B, B to Y |
vme_data_oe_n_o <= '0'; -- Driven IFF DIR = 1
vme_addr_oe_n_o <= '0'; -- Driven IFF DIR = 1
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Access Mode Decoders -- Access Mode Decoders
...@@ -268,15 +267,23 @@ begin ...@@ -268,15 +267,23 @@ begin
variable addr_word_incr : natural range 0 to 7; variable addr_word_incr : natural range 0 to 7;
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
if rst_n_i = '0' or bridge_addr_req_i = '1' then if rst_n_i = '0' or vme_as_n_i = '1' then
-- FSM reset after power up, -- FSM reset after power up,
-- software reset, manually reset, -- software reset, manually reset,
-- on rising edge of AS. -- on rising edge of AS.
s_conf_req <= '0'; s_conf_req <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
-- VME Bridge -- VME
vme_dtack_oe_o <= '0';
vme_dtack_n_o <= '1';
vme_data_dir_o <= '0';
vme_addr_dir_o <= '0';
vme_berr_n_o <= '1';
vme_addr_o <= (others => '0');
vme_lword_n_o <= '1';
vme_data_o <= (others => '0');
vme_iackout_n_o <= '1';
s_dataPhase <= '0'; s_dataPhase <= '0';
s_MBLT_Data <= '0'; s_MBLT_Data <= '0';
s_mainFSMstate <= IDLE; s_mainFSMstate <= IDLE;
...@@ -287,9 +294,8 @@ begin ...@@ -287,9 +294,8 @@ begin
wb_stb_o <= '0'; wb_stb_o <= '0';
s_err <= '0'; s_err <= '0';
s_ADDRlatched <= bridge_addr_i; s_ADDRlatched <= (others => '0');
s_LWORDlatched_n <= bridge_addr_lword_n_i; s_AMlatched <= (others => '0');
s_AMlatched <= bridge_addr_am_i;
s_vme_addr_reg <= (others => '0'); s_vme_addr_reg <= (others => '0');
s_vme_addr_dir <= '0'; s_vme_addr_dir <= '0';
...@@ -301,22 +307,27 @@ begin ...@@ -301,22 +307,27 @@ begin
else else
s_conf_req <= '0'; s_conf_req <= '0';
decode_start_o <= '0'; decode_start_o <= '0';
vme_dtack_oe_o <= '0';
vme_dtack_n_o <= '1';
vme_data_dir_o <= '0';
vme_addr_dir_o <= '0';
vme_berr_n_o <= '1';
vme_iackout_n_o <= '1';
irq_ack_o <= '0'; irq_ack_o <= '0';
bridge_write_ack_o <= '0';
case s_mainFSMstate is case s_mainFSMstate is
when IDLE => when IDLE =>
-- Can only be here if vme_as_n_i has fallen to 0, which starts a
-- cycle.
assert vme_as_n_i = '0';
-- Store ADDR, AM and LWORD -- Store ADDR, AM and LWORD
if bridge_addr_req_i = '1' then s_ADDRlatched <= vme_addr_i;
s_ADDRlatched <= bridge_addr_i; s_LWORDlatched_n <= vme_lword_n_i;
s_LWORDlatched_n <= bridge_addr_lword_n_i; s_AMlatched <= vme_am_i;
s_AMlatched <= bridge_addr_am_i;
end if;
if bridge_aux_iack_n_i = '1' and bridge_aux_valid_i = '1' then if vme_iack_n_i = '1' then
-- ANSI/VITA 1-1994 Rule 2.11 -- ANSI/VITA 1-1994 Rule 2.11
-- Slaves MUST NOT respond to DTB cycles when IACK* is low. -- Slaves MUST NOT respond to DTB cycles when IACK* is low.
s_mainFSMstate <= REFORMAT_ADDRESS; s_mainFSMstate <= REFORMAT_ADDRESS;
...@@ -325,7 +336,6 @@ begin ...@@ -325,7 +336,6 @@ begin
s_mainFSMstate <= IRQ_CHECK; s_mainFSMstate <= IRQ_CHECK;
end if; end if;
when REFORMAT_ADDRESS => when REFORMAT_ADDRESS =>
-- Reformat address according to the mode (A16, A24, A32) -- Reformat address according to the mode (A16, A24, A32)
-- FIXME: not needed if ADEM are correctly reduced to not compare -- FIXME: not needed if ADEM are correctly reduced to not compare
...@@ -356,14 +366,14 @@ begin ...@@ -356,14 +366,14 @@ begin
-- capability. -- capability.
if s_LWORDlatched_n = '0' and s_ADDRlatched(1) = '1' then if s_LWORDlatched_n = '0' and s_ADDRlatched(1) = '1' then
-- unaligned. -- unaligned.
s_mainFSMstate <= IDLE; s_mainFSMstate <= WAIT_END;
else else
if s_ADDRlatched(23 downto 19) = bar_i if s_ADDRlatched(23 downto 19) = bar_i
and s_AMlatched = c_AM_CR_CSR and s_AMlatched = c_AM_CR_CSR
then then
-- conf_sel = '1' it means CR/CSR space addressed -- conf_sel = '1' it means CR/CSR space addressed
s_conf_sel <= '1'; s_conf_sel <= '1';
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= WAIT_FOR_DS;
else else
s_mainFSMstate <= DECODE_ACCESS; s_mainFSMstate <= DECODE_ACCESS;
decode_start_o <= '1'; decode_start_o <= '1';
...@@ -374,13 +384,11 @@ begin ...@@ -374,13 +384,11 @@ begin
-- Check if this slave board is addressed. -- Check if this slave board is addressed.
-- Wait for DS in parallel. -- Wait for DS in parallel.
if vme_ds_n_i /= "11" then
if bridge_write_req_i = '1' then s_WRITElatched_n <= vme_write_n_i;
s_WRITElatched_n <= bridge_write_write_n_i; if s_DS_latch_count /= 0 then
s_DS_latch_count <= s_DS_latch_count - 1;
end if; end if;
if bridge_read_req_i = '1' then
s_WRITElatched_n <= bridge_read_write_n_i;
end if; end if;
if decode_done_i = '1' then if decode_done_i = '1' then
...@@ -390,43 +398,47 @@ begin ...@@ -390,43 +398,47 @@ begin
-- Keep only the local part of the address. -- Keep only the local part of the address.
s_vme_addr_reg <= addr_decoder_i; s_vme_addr_reg <= addr_decoder_i;
if vme_ds_n_i = "11" then
s_mainFSMstate <= WAIT_FOR_DS;
else
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= LATCH_DS;
end if;
else else
-- Another board will answer; wait here the rising edge on -- Another board will answer; wait here the rising edge on
-- vme_as_i (done by top if). -- vme_as_i (done by top if).
s_mainFSMstate <= IDLE; s_mainFSMstate <= WAIT_END;
end if; end if;
else else
-- Not yet decoded. -- Not yet decoded.
s_mainFSMstate <= DECODE_ACCESS; s_mainFSMstate <= DECODE_ACCESS;
end if; end if;
when WAIT_FOR_DS =>
-- wait until DS /= "11"
-- Note: before entering this state, s_DS_latch_count must be set.
if vme_ds_n_i /= "11" then
-- ANSI/VITA 1-1994 Table 4-1
when LATCH_DS => -- For interrupts ack, the handler MUST NOT drive WRITE* low
s_WRITElatched_n <= vme_write_n_i;
if bridge_read_req_i = '1' THEN if s_DS_latch_count /= 0 then
s_WRITElatched_n <= bridge_read_write_n_i; s_DS_latch_count <= s_DS_latch_count - 1;
s_DSlatched_n <= bridge_read_ds_n_i;
bridge_read_ack_o <= '1';
end if; end if;
s_mainFSMstate <= LATCH_DS;
if bridge_write_req_i = '1' then else
s_locDataIn(63 downto 33) <= bridge_write_data_i(63 downto 33); s_mainFSMstate <= WAIT_FOR_DS;
s_LWORDlatched_n <= bridge_write_data_i(32);
s_vme_data_reg <= bridge_write_data_i(31 downto 0);
s_WRITElatched_n <= bridge_write_write_n_i;
s_DSlatched_n <= bridge_write_ds_n_i;
bridge_write_ack_o <= '1';
end if; end if;
when LATCH_DS =>
-- This state is necessary indeed the VME master can assert the -- This state is necessary indeed the VME master can assert the
-- DS lines not at the same time. -- DS lines not at the same time.
-- ANSI/VITA 1-1994 Rule 2.53a
-- During all read cycles [...], the responding slave MUST NOT
-- drive the D[] lines until DSA* goes low.
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= '0';
if s_transferType = MBLT then if s_transferType = MBLT then
s_dataPhase <= '1'; s_dataPhase <= '1';
...@@ -436,8 +448,7 @@ begin ...@@ -436,8 +448,7 @@ begin
s_dataPhase <= '0'; s_dataPhase <= '0';
end if; end if;
if bridge_write_req_i = '1' or bridge_read_req_i = '1' then if s_DS_latch_count = 0 or s_transferType = MBLT then
if s_irq_sel = '1' then if s_irq_sel = '1' then
s_mainFSMstate <= DATA_TO_BUS; s_mainFSMstate <= DATA_TO_BUS;
elsif s_transferType = MBLT and s_MBLT_Data = '0' then elsif s_transferType = MBLT and s_MBLT_Data = '0' then
...@@ -447,11 +458,22 @@ begin ...@@ -447,11 +458,22 @@ begin
else else
s_mainFSMstate <= CHECK_TRANSFER_TYPE; s_mainFSMstate <= CHECK_TRANSFER_TYPE;
end if; end if;
end if;
-- Read DS (which is delayed to avoid metastability).
s_DSlatched_n <= vme_ds_n_i;
when CHECK_TRANSFER_TYPE => -- Read DATA (which are stable)
s_locDataIn(63 downto 33) <= vme_addr_i;
s_LWORDlatched_n <= vme_lword_n_i;
s_vme_data_reg <= vme_data_i;
else
s_mainFSMstate <= LATCH_DS;
s_DS_latch_count <= s_DS_latch_count - 1;
end if;
when CHECK_TRANSFER_TYPE =>
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= '0';
s_dataPhase <= s_dataPhase; s_dataPhase <= s_dataPhase;
-- vme_addr is an output during MBLT *read* data transfer. -- vme_addr is an output during MBLT *read* data transfer.
...@@ -489,7 +511,7 @@ begin ...@@ -489,7 +511,7 @@ begin
-- capability. -- capability.
if s_vme_lword_n_reg = '0' and s_DSlatched_n /= "00" then if s_vme_lword_n_reg = '0' and s_DSlatched_n /= "00" then
-- unaligned. -- unaligned.
s_mainFSMstate <= IDLE; s_mainFSMstate <= WAIT_END;
else else
s_mainFSMstate <= MEMORY_REQ; s_mainFSMstate <= MEMORY_REQ;
s_conf_req <= s_conf_sel; s_conf_req <= s_conf_sel;
...@@ -497,15 +519,27 @@ begin ...@@ -497,15 +519,27 @@ begin
-- Start WB cycle. -- Start WB cycle.
wb_cyc_o <= s_card_sel; wb_cyc_o <= s_card_sel;
wb_stb_o <= s_card_sel; wb_stb_o <= s_card_sel;
s_stall <= '1'; -- Can stall
s_err <= '0'; s_err <= '0';
end if; end if;
when MEMORY_REQ => when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to -- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_conf_req signal -- generate a pulse on s_conf_req signal
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
-- Assert STB if stall was asserted. -- Assert STB if stall was asserted.
wb_stb_o <= s_card_sel and wb_stall_i; case g_WB_MODE is
when CLASSIC =>
-- Maintain STB.
wb_stb_o <= s_card_sel;
when PIPELINED =>
-- Maintain STB if stall was set in the previous cycle.
wb_stb_o <= s_card_sel and s_stall and wb_stall_i;
end case;
s_stall <= s_stall and wb_stall_i;
if s_conf_sel = '1' if s_conf_sel = '1'
or (s_card_sel = '1' and (wb_ack_i = '1' or wb_err_i = '1')) or (s_card_sel = '1' and (wb_ack_i = '1' or wb_err_i = '1'))
...@@ -569,69 +603,75 @@ begin ...@@ -569,69 +603,75 @@ begin
if wb_ack_i = '0' then if wb_ack_i = '0' then
wb_stb_o <= '1'; wb_stb_o <= '1';
s_stall <= '1';
s_mainFSMstate <= MEMORY_REQ; s_mainFSMstate <= MEMORY_REQ;
else else
s_mainFSMstate <= MEMORY_PAUSE; s_mainFSMstate <= MEMORY_PAUSE;
end if; end if;
when DATA_TO_BUS => -- entered upon successdful read or on s_irq_sel when DATA_TO_BUS =>
vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
bridge_cpl_req_o <= '1'; vme_addr_o <= s_locDataOut(63 downto 33);
bridge_cpl_data_dir_o <= s_WRITElatched_n or s_irq_sel; vme_lword_n_o <= s_locDataOut(32);
bridge_cpl_addr_dir_o <= s_vme_addr_dir; vme_data_o <= s_locDataOut(31 downto 0);
if s_card_sel = '1' and s_err = '1' then -- ANSI/VITA 1-1994 Rule 2.54a
bridge_cpl_berr_o <= '1'; -- During all read cycles, the responding Slave MUST NOT drive
else -- DTACK* low before it drives D[].
bridge_cpl_dtack_n_o <= '0'; s_mainFSMstate <= DTACK_LOW;
end if;
bridge_cpl_has_data_o <= '1'; when DTACK_LOW =>
bridge_cpl_data_o <= s_locDataOut; vme_dtack_oe_o <= '1';
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
if s_irq_sel = '1' then -- Set DTACK (or retry or berr)
s_mainFSMstate <= IDLE; if s_card_sel = '1' and s_err = '1' then
elsif s_transferType = SINGLE then vme_berr_n_o <= '0';
-- Cycle should be finished, but allow another access at
-- the same address (RMW).
s_mainFSMstate <= LATCH_DS;
else
if s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase.
s_mainFSMstate <= LATCH_DS;
s_MBLT_Data <= '1';
else else
-- Block vme_dtack_n_o <= '0';
s_mainFSMstate <= INCREMENT_ADDR;
end if;
end if; end if;
when DTACK_LOW =>
-- ANSI/VITA 1-1994 Rule 2.57 -- ANSI/VITA 1-1994 Rule 2.57
-- Once the responding Slave has driven DTACK* or BERR* low, it -- Once the responding Slave has driven DTACK* or BERR* low, it
-- MUST NOT release them or drive DTACK* high until it detects -- MUST NOT release them or drive DTACK* high until it detects
-- both DS0* and DS1* high. -- both DS0* and DS1* high.
if vme_ds_n_i = "11" then
vme_data_dir_o <= '0';
vme_berr_n_o <= '1';
-- Rescind DTACK.
vme_dtack_n_o <= '1';
-- DS latch counter
s_DS_latch_count <= to_unsigned (c_num_latchDS, 3);
if s_irq_sel = '1' then if s_irq_sel = '1' then
s_mainFSMstate <= IDLE; s_mainFSMstate <= WAIT_END;
elsif s_transferType = SINGLE then elsif s_transferType = SINGLE then
-- Cycle should be finished, but allow another access at -- Cycle should be finished, but allow another access at
-- the same address (RMW). -- the same address (RMW).
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= WAIT_FOR_DS;
else else
if s_transferType = MBLT and s_MBLT_Data = '0' then if s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase. -- MBLT: end of address phase.
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= WAIT_FOR_DS;
s_MBLT_Data <= '1'; s_MBLT_Data <= '1';
else else
-- Block -- Block
s_mainFSMstate <= INCREMENT_ADDR; s_mainFSMstate <= INCREMENT_ADDR;
end if; end if;
end if; end if;
else
s_mainFSMstate <= DTACK_LOW;
end if;
when INCREMENT_ADDR => when INCREMENT_ADDR =>
vme_dtack_oe_o <= '1';
vme_addr_dir_o <= s_vme_addr_dir;
if s_vme_lword_n_reg = '0' then if s_vme_lword_n_reg = '0' then
if s_transferType = MBLT then if s_transferType = MBLT then
...@@ -654,10 +694,10 @@ begin ...@@ -654,10 +694,10 @@ begin
-- MBLT --> limit = 2048 bytes (rule 2.78 ANSI/VITA 1-1994) -- MBLT --> limit = 2048 bytes (rule 2.78 ANSI/VITA 1-1994)
s_vme_addr_reg (11 downto 1) <= std_logic_vector s_vme_addr_reg (11 downto 1) <= std_logic_vector
(unsigned(s_vme_addr_reg (11 downto 1)) + addr_word_incr); (unsigned(s_vme_addr_reg (11 downto 1)) + addr_word_incr);
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= WAIT_FOR_DS;
when IRQ_CHECK => when IRQ_CHECK =>
if bridge_aux_valid_i = '1' and bridge_aux_iackin_n_i = '0'then if vme_iackin_n_i = '0' then
if s_ADDRlatched(3 downto 1) = int_level_i if s_ADDRlatched(3 downto 1) = int_level_i
and irq_pending_i = '1' and irq_pending_i = '1'
then then
...@@ -667,12 +707,10 @@ begin ...@@ -667,12 +707,10 @@ begin
s_irq_sel <= '1'; s_irq_sel <= '1';
irq_ack_o <= '1'; irq_ack_o <= '1';
s_mainFSMstate <= LATCH_DS; s_mainFSMstate <= WAIT_FOR_DS;
else else
-- Pass -- Pass
bridge_aux_iackout_n_o <= '0'; vme_iackout_n_o <= '0';
--vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS; s_mainFSMstate <= IRQ_PASS;
end if; end if;
else else
...@@ -681,16 +719,26 @@ begin ...@@ -681,16 +719,26 @@ begin
when IRQ_PASS => when IRQ_PASS =>
-- Will stay here until AS is released. -- Will stay here until AS is released.
bridge_aux_iackout_n_o <= '0'; vme_iackout_n_o <= '0';
--vme_iackout_n_o <= '0';
s_mainFSMstate <= IRQ_PASS; s_mainFSMstate <= IRQ_PASS;
when WAIT_END =>
-- Will stay here until AS is released.
s_mainFSMstate <= WAIT_END;
when others =>
-- No-op, wait until AS is released.
s_mainFSMstate <= WAIT_END;
end case; end case;
end if; end if;
end if; end if;
end process; end process;
-- Retry is not supported
vme_retry_n_o <= '1';
vme_retry_oe_o <= '0';
-- WB Master -- WB Master
with g_WB_GRANULARITY select with g_WB_GRANULARITY select
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD, wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
......
hdl/rtl/vme_bus_bridge.vhd
View file @ 2460adc3
...@@ -8,8 +8,8 @@ ...@@ -8,8 +8,8 @@
-- --
-- description: -- description:
-- --
-- This block acts as interface between the VMEbus and the CR/CSR space or -- Slighthtly hacked version of the vme_bus module for the purpose of testing
-- WB bus. -- the inter-fpga VME serial bridge.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE -- GNU LESSER GENERAL PUBLIC LICENSE
......
hdl/rtl/xvme64x_bridge_serdes.vhd 0 → 100644
View file @ 2460adc3
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity xvme64x_bridge_serdes is
generic (
g_mode : t_bridge_serdes_mode := MASTER;
g_platform : string := "spartan6";
g_SERDES_RX_DELAY_TAPS : integer:= 0;
g_CLOCK_PERIOD : integer := 16
);
port (
clk_125m_i : in std_logic := '0';
rst_n_i : in std_logic := '0';
bridge_d_i : in std_logic_vector(15 downto 0);
bridge_frame_i : in std_logic;
bridge_d_o : out std_logic_vector(15 downto 0);
bridge_frame_o : out std_logic;
bridge_clk_o : out std_logic;
bridge_rst_n_o : out std_logic;
ser_clk_p_i : in std_logic := '0';
ser_clk_n_i : in std_logic := '0';
ser_clk_p_o : out std_logic;
ser_clk_n_o : out std_logic;
ser_tx_o : out std_logic_vector(4 downto 0);
ser_rx_i : in std_logic_vector(4 downto 0)
);
end xvme64x_bridge_serdes;
architecture rtl of xvme64x_bridge_serdes is
signal ser_clk_buf : std_logic;
signal clk_125m_0 : std_logic;
signal clk_500m_0 : std_logic;
signal pllout_clk_fb : std_logic;
signal pllout_clk_125m_0 : std_logic;
signal clk_500m_serdes : std_logic;
signal serdes_strobe : std_logic;
signal pll_locked : std_logic;
type t_serdes_par_data is array(0 to 4) of std_logic_vector(3 downto 0);
signal ser_rx_predelay, ser_rx_postdelay : std_logic_vector(4 downto 0);
signal ser_tx_predelay, ser_tx_postdelay : std_logic_vector(4 downto 0);
signal par_rx, par_tx : t_serdes_par_data;
signal io_reset : std_logic;
signal ser_clk_out_prebuf : std_logic;
signal serdes_rx_bitslip : std_logic;
signal BITSLIP_cnt : unsigned(3 downto 0);
begin
io_reset <= not rst_n_i;
gen1 : if g_mode = MASTER generate
U_clk_buf : IBUFGDS
generic map (
DIFF_TERM => TRUE
)
port map (
O => ser_clk_buf,
I => ser_clk_p_i,
IB => ser_clk_n_i
);
bridge_clk_o <= ser_clk_buf;
bridge_rst_n_o <= rst_n_i;
end generate gen1;
gen2 : if g_mode /= MASTER generate
ser_clk_buf <= clk_125m_i;
end generate gen2;
-- PLL for producing 125 MHz App clock
U_App_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2, -- 500 MHz (IOSERDES)
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 180.000, -- 125 MHz (180 deg)
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb,
CLKOUT0 => clk_500m_0,
CLKOUT1 => pllout_clk_125m_0,
CLKOUT2 => open, --pllout_clk_sys,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pll_locked,
RST => '0',
CLKFBIN => pllout_clk_fb,
CLKIN => ser_clk_buf);
U_clk_0_buf : BUFG
port map (
O => clk_125m_0,
I => pllout_clk_125m_0);
U_BufPLL : BUFPLL
generic map (
DIVIDE => 4
)
port map (
PLLIN => clk_500m_0,
LOCKED => pll_locked,
GCLK => clk_125m_0,
SERDESSTROBE => serdes_strobe,
IOCLK => clk_500m_serdes,
LOCK => open
);
gen_serdeses : for i in 0 to 4 generate
cmp_ibuf : IBUF
generic map (
IOSTANDARD => "LVCMOS33")
port map (
I => ser_rx_i(i),
O => ser_rx_predelay(i));
cmp_obuf : OBUF
generic map (
IOSTANDARD => "LVCMOS33")
port map (
O => ser_tx_o(i),
I => ser_tx_postdelay(i));
-- Instantiate the delay primitive
-----------------------------------
cmp_iodelay : IODELAY2
generic map (
DATA_RATE => "SDR",
IDELAY_VALUE => g_SERDES_RX_DELAY_TAPS,
IDELAY_TYPE => "FIXED",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75)
port map (
-- required datapath
IDATAIN => ser_rx_predelay(i),
DATAOUT => ser_rx_postdelay(i),
T => '1',
-- inactive data connections
DATAOUT2 => open,
DOUT => open,
ODATAIN => '0',
TOUT => open,
-- connect up the clocks
IOCLK0 => '0', -- No calibration needed
IOCLK1 => '0', -- No calibration needed
-- Tie of the variable delay programming
CLK => '0',
CAL => '0',
INC => '0',
CE => '0',
BUSY => open,
RST => '0');
cmp_iserdes : ISERDES2
generic map (
DATA_RATE => "SDR",
DATA_WIDTH => 4,
INTERFACE_TYPE => "RETIMED",
SERDES_MODE => "NONE",
BITSLIP_ENABLE => true)
port map (
Q1 => par_rx(i)(3),
Q2 => par_rx(i)(2),
Q3 => par_rx(i)(1),
Q4 => par_rx(i)(0),
SHIFTOUT => open,
INCDEC => open,
VALID => open,
BITSLIP => serdes_rx_bitslip,
CE0 => '1',
CLK0 => clk_500m_serdes,
CLK1 => '0',
CLKDIV => clk_125m_0,
D => ser_rx_postdelay(i),
IOCE => serdes_strobe,
RST => io_reset,
SHIFTIN => '0' );
cmp_oserdes : OSERDES2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_OT => "SDR",
TRAIN_PATTERN => 0,
DATA_WIDTH => 4,
SERDES_MODE => "NONE",
OUTPUT_MODE => "SINGLE_ENDED")
port map (
D1 => par_tx(i)(3),
D2 => par_tx(i)(2),
D3 => par_tx(i)(1),
D4 => par_tx(i)(0),
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '1',
SHIFTIN2 => '1',
SHIFTIN3 => '1',
SHIFTIN4 => '1',
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TRAIN => '0',
OCE => '1',
CLK0 => clk_500m_serdes,
CLK1 => '0',
CLKDIV => clk_125m_0,
OQ => ser_tx_postdelay(i),
TQ => open,
IOCE => serdes_strobe,
TCE => '1',
RST => IO_RESET);
end generate gen_serdeses;
gen3: if g_mode = SLAVE generate
cmp_oserdes_clk : OSERDES2
generic map (
DATA_RATE_OQ => "SDR",
DATA_RATE_OT => "SDR",
TRAIN_PATTERN => 0,
DATA_WIDTH => 4,
SERDES_MODE => "NONE",
OUTPUT_MODE => "SINGLE_ENDED")
port map (
D1 => '0',
D2 => '0',
D3 => '1',
D4 => '1',
T1 => '0',
T2 => '0',
T3 => '0',
T4 => '0',
SHIFTIN1 => '1',
SHIFTIN2 => '1',
SHIFTIN3 => '1',
SHIFTIN4 => '1',
SHIFTOUT1 => open,
SHIFTOUT2 => open,
SHIFTOUT3 => open,
SHIFTOUT4 => open,
TRAIN => '0',
OCE => '1',
CLK0 => clk_500m_serdes,
CLK1 => '0',
CLKDIV => clk_125m_0,
OQ => ser_clk_out_prebuf,
TQ => open,
IOCE => serdes_strobe,
TCE => '1',
RST => IO_RESET);
OBUFDS_clk: OBUFDS
generic map (
IOSTANDARD => "DEFAULT",
SLEW => "FAST")
port map (
O => ser_clk_p_o,
OB => ser_clk_n_o,
I => ser_clk_out_prebuf);
end generate gen3;
gen_serdes_data : for i in 0 to 3 generate
par_tx(i)(0) <= bridge_d_i(i*4+0);
par_tx(i)(1) <= bridge_d_i(i*4+1);
par_tx(i)(2) <= bridge_d_i(i*4+2);
par_tx(i)(3) <= bridge_d_i(i*4+3);
bridge_d_o(i*4+0) <= par_rx(i)(0);
bridge_d_o(i*4+1) <= par_rx(i)(1);
bridge_d_o(i*4+2) <= par_rx(i)(2);
bridge_d_o(i*4+3) <= par_rx(i)(3);
bridge_frame_o <= par_rx(4)(0);
par_tx(4)(0) <= bridge_frame_i;
par_tx(4)(1) <= '0';
par_tx(4)(2) <= '0';
par_tx(4)(3) <= '0';
end generate gen_serdes_data;
p_serdes_bitslip : process(clk_125m_0, rst_n_i)
begin
if rst_n_i = '0' then
BITSLIP_cnt <= (others => '0');
serdes_rx_bitslip <= '0';
elsif rising_edge(clk_125m_0) then
if BITSLIP_cnt = 0 then
if par_rx(4) /= "0000" and par_rx(4) /= "0001" then
serdes_rx_bitslip <= '1';
BITSLIP_cnt <= to_unsigned(10, 4);
end if;
else
serdes_rx_bitslip <= '0';
BITSLIP_cnt <= BITSLIP_cnt - 1;
end if;
end if;
end process;
end rtl;
hdl/rtl/xvme64x_core_master.vhd
View file @ 2460adc3
...@@ -53,9 +53,9 @@ entity xvme64x_core_master is ...@@ -53,9 +53,9 @@ entity xvme64x_core_master is
afpga_clk_i : in std_logic; afpga_clk_i : in std_logic;
afpga_rst_n_i : in std_logic; afpga_rst_n_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0); afpga_d_i : in std_logic_vector(15 downto 0);
afpga_frame_i : in std_logic; afpga_frame_i : in std_logic;
afpga_d_o : out std_logic_vector(7 downto 0); afpga_d_o : out std_logic_vector(15 downto 0);
afpga_frame_o : out std_logic afpga_frame_o : out std_logic
); );
...@@ -263,7 +263,7 @@ begin ...@@ -263,7 +263,7 @@ begin
s_ga <= not vme_i.ga(4 downto 0) when s_ga_parity = '1' else '1' & x"e"; s_ga <= not vme_i.ga(4 downto 0) when s_ga_parity = '1' else '1' & x"e";
bridge_master_1: entity work.bridge_master inst_serial_bridge: entity work.serial_bridge_master
generic map ( generic map (
g_clock_period => g_clock_period) g_clock_period => g_clock_period)
port map ( port map (
......
hdl/rtl/xvme64x_core_slave.vhd
View file @ 2460adc3
...@@ -44,10 +44,6 @@ entity xvme64x_core_slave is ...@@ -44,10 +44,6 @@ entity xvme64x_core_slave is
-- Clock period (ns). Used for DS synchronization. A value is required. -- Clock period (ns). Used for DS synchronization. A value is required.
g_CLOCK_PERIOD : natural; g_CLOCK_PERIOD : natural;
-- Enables 'bridged' mode - with reduced pin count interface (bridge_xxx ports)
-- and an external system FPGA acting as a VME I/O expander.
g_BRIDGED_MODE : boolean := false;
-- Consider AM field of ADER to decode addresses. This is what the VME64x -- Consider AM field of ADER to decode addresses. This is what the VME64x
-- standard says. However, for compatibility with previous implementations -- standard says. However, for compatibility with previous implementations
-- (or to reduce resources), it is possible for a decoder to allow all AM -- (or to reduce resources), it is possible for a decoder to allow all AM
...@@ -115,14 +111,11 @@ entity xvme64x_core_slave is ...@@ -115,14 +111,11 @@ entity xvme64x_core_slave is
wb_i : in t_wishbone_master_in; wb_i : in t_wishbone_master_in;
wb_o : out t_wishbone_master_out; wb_o : out t_wishbone_master_out;
-- Bridge I/F -- Bridge I/F to the SerDes
bridge_clk_o : out std_logic;
bridge_rst_n_o : out std_logic;
bridge_frame_o : out std_logic; bridge_frame_o : out std_logic;
bridge_d_o : out std_logic_vector(7 downto 0); bridge_d_o : out std_logic_vector(15 downto 0);
bridge_frame_i : in std_logic := '0'; bridge_frame_i : in std_logic := '0';
bridge_d_i : in std_logic_vector(7 downto 0) := x"00"; bridge_d_i : in std_logic_vector(15 downto 0) := x"0000";
-- Interrupt input from the master side. -- Interrupt input from the master side.
-- Previously it was part of the wishbone interface, but is now separate -- Previously it was part of the wishbone interface, but is now separate
...@@ -274,18 +267,17 @@ begin ...@@ -274,18 +267,17 @@ begin
severity failure; severity failure;
end generate; end generate;
bridge_clk_o <= clk_i;
bridge_rst_n_o <= rst_n_i;
s_reset_n <= rst_n_i; s_reset_n <= rst_n_i;
bridge_slave_1: entity work.bridge_slave inst_serial_bridge : entity work.serial_bridge_slave
generic map ( generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD) g_CLOCK_PERIOD => g_CLOCK_PERIOD)
port map ( port map (
sfpga_rst_n_i => rst_n_i, sfpga_rst_n_i => rst_n_i,
sfpga_clk_i => clk_i, sfpga_clk_i => clk_i,
sfpga_d_i => bridge_d_i, sfpga_d_i => bridge_d_i,
sfpga_frame_i => bridge_frame_i, sfpga_frame_i => bridge_frame_i,
sfpga_d_o => bridge_d_o, sfpga_d_o => bridge_d_o,
......
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