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VME64x core
Commit 6f359655 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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bridge: reads/writes work, wip

parent e8b874db
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hdl/rtl/Manifest.py
View file @ 6f359655
files = [ "vme64x_core.vhd",
"xvme64x_core_master.vhd",
"xvme64x_core_slave.vhd",
"vme64x_pkg.vhd",
"vme_bus.vhd",
"vme_bus_bridge.vhd",
"vme_cr_csr_space.vhd",
"vme_funct_match.vhd",
"vme_irq_controller.vhd",
"vme_user_csr.vhd",
"vme_sfpga_bridge.vhd",
"xvme64x_core.vhd"]
"bridge_master.vhd",
"bridge_slave.vhd"
# "xvme64x_core.vhd"
]
hdl/rtl/bridge_master.vhd 0 → 100644
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hdl/rtl/bridge_slave.vhd 0 → 100644
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hdl/rtl/vme_bus_bridge.vhd 0 → 100644
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hdl/rtl/vme_cr_csr_space.vhd
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......@@ -116,12 +116,12 @@ entity vme_cr_csr_space is
g_END_USER_CSR : std_logic_vector(23 downto 0);
g_BEG_SN : std_logic_vector(23 downto 0);
g_END_SN : std_logic_vector(23 downto 0);
g_BRIDGED_MODE : boolean;
g_DECODER : t_vme64x_decoder_arr);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
vme_aux_valid_i : in std_logic;
vme_ga_i : in std_logic_vector(4 downto 0);
vme_berr_n_i : in std_logic;
bar_o : out std_logic_vector(4 downto 0);
......@@ -141,13 +141,7 @@ entity vme_cr_csr_space is
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader_o : out t_ader_array;
bridge_aux_valid_i : in std_logic;
bridge_aux_ga_i : in std_logic_vector(4 downto 0)
);
ader_o : out t_ader_array);
end vme_cr_csr_space;
architecture rtl of vme_cr_csr_space is
......@@ -202,7 +196,7 @@ architecture rtl of vme_cr_csr_space is
signal s_cram_waddr : unsigned(18 downto 2);
signal s_cram_raddr : unsigned(18 downto 2);
signal s_cram_we : std_logic;
signal s_vme_aux_valid_d : std_logic;
-- Addresses
subtype crcsr_addr is unsigned(18 downto 2);
constant c_BEG_CR : crcsr_addr := to_unsigned(16#00000# / 4, 17);
......@@ -332,6 +326,9 @@ begin
variable csr_boff : unsigned(3 downto 2);
begin
if rising_edge(clk_i) then
s_vme_aux_valid_d <= vme_aux_valid_i;
if rst_n_i = '0' then
s_reg_bar <= vme_ga_i & "000";
s_reg_bit_reg <= x"00";
......@@ -339,8 +336,9 @@ begin
s_reg_usr_bit_reg <= x"00";
s_reg_ader <= (others => x"00000000");
else
if g_BRIDGED_MODE and bridge_aux_valid_i = '1' then
s_reg_bar <= bridge_aux_ga_i & "000";
if s_vme_aux_valid_d = '0' and vme_aux_valid_i = '1' then
s_reg_bar <= vme_ga_i & "000";
end if;
if we_i = '1' and s_csr_access = '1' then
......
hdl/rtl/vme_sfpga_bridge.vhd
View file @ 6f359655
......@@ -8,7 +8,7 @@ use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity vme_sfpga_bridge is
entity bridge_master is
generic(
g_clock_period : integer
);
......@@ -22,62 +22,57 @@ entity vme_sfpga_bridge is
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
-- address channel
addr_req_o : out std_logic;
addr_o : out std_logic_vector(31 downto 1);
addr_am_o : out std_logic_vector(5 downto 0);
addr_lword_n_o : out std_logic;
-- data channel (write)
write_req_o : out std_logic;
write_ack_i : in std_logic;
write_ds_n_o : out std_logic_vector(1 downto 0);
write_data_o : out std_logic_vector(63 downto 0);
write_dtack_n_i : in std_logic;
write_berr_i : in std_logic;
write_write_n_o : out std_logic;
-- data channel (read)
read_req_o : out std_logic := '0';
read_ack_i : in std_logic;
read_ds_n_o : out std_logic_vector(1 downto 0);
read_write_n_o : out std_logic;
-- data channel (read/write completion)
cpl_req_i : in std_logic;
cpl_ack_o : out std_logic;
cpl_has_data_i : in std_logic;
cpl_data_i : out std_logic_vector(63 downto 0) := x"0000000000000000";
cpl_dtack_n_i : in std_logic := '0';
cpl_berr_i : in std_logic := '0';
aux_valid_o : out std_logic;
aux_ga_o : out std_logic_vector(5 downto 0);
aux_iackin_n_o : out std_logic;
aux_iack_n_o : out std_logic;
aux_irq_n_i : in std_logic_vector(7 downto 1);
aux_iackout_n_i : in std_logic
-- aux channel
mem_req_i : in std_logic;
mem_is_blt_i : in std_logic;
mem_ack_o : out std_logic;
mem_err_o : out std_logic;
mem_we_i : in std_logic;
mem_addr_i : in std_logic_vector(31 downto 0);
mem_data_o : out std_logic_vector(31 downto 0);
mem_data_i : in std_logic_vector(31 downto 0);
mem_sel_i : in std_logic_vector(3 downto 0);
-- Function decoder
addr_decoder_i : in std_logic_vector(31 downto 1);
addr_decoder_o : out std_logic_vector(31 downto 1);
decode_start_i : in std_logic;
decode_done_o : out std_logic;
am_i : in std_logic_vector( 5 downto 0);
decode_sel_o : out std_logic;
-- CR/CSR space signals:
cr_csr_addr_i : in std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
cr_csr_data_o : out std_logic_vector( 7 downto 0);
cr_csr_we_i : in std_logic;
cr_csr_req_i : in std_logic;
1 cr_csr_done_o : out std_logic;
module_enable_o : out std_logic;
bar_o : out std_logic_vector( 4 downto 0);
-- Interrupts
int_level_o : out std_logic_vector( 2 downto 0);
int_vector_o : out std_logic_vector( 7 downto 0);
irq_pending_o : out std_logic;
irq_ack_i : in std_logic
);
end vme_sfpga_bridge;
end bridge_master;
architecture rtl of vme_sfpga_bridge is
architecture rtl of bridge_master is
constant c_tag_addr : std_logic_vector(7 downto 0) := x"a0";
constant c_tag_read : std_logic_vector(7 downto 0) := x"a1";
constant c_tag_write : std_logic_vector(7 downto 0) := x"a2";
constant c_tag_read_cpl : std_logic_vector(7 downto 0) := x"a3";
constant c_tag_irq : std_logic_vector(7 downto 0) := x"a4";
constant c_tag_iackin : std_logic_vector(7 downto 0) := x"a5";
constant c_tag_iackout : std_logic_vector(7 downto 0) := x"a6";
constant c_tag_aux : std_logic_vector(7 downto 0) := x"a7";
constant c_tag_csr_req : std_logic_vector(3 downto 0) := x"0";
constant c_tag_csr_rsp : std_logic_vector(3 downto 0) := x"1";
constant c_tag_config : std_logic_vector(3 downto 0) := x"2";
constant c_tag_decode_req : std_logic_vector(3 downto 0) := x"2";
constant c_tag_read_cpl : std_logic_vector(3 downto 0) := x"3";
constant c_tag_irq : std_logic_vector(3 downto 0) := x"4";
constant c_tag_iackin : std_logic_vector(3 downto 0) := x"5";
constant c_tag_iackout : std_logic_vector(3 downto 0) := x"6";
constant c_tag_aux : std_logic_vector(3 downto 0) := x"7";
signal afpga_dout : std_logic_vector(15 downto 0);
signal afpga_din : std_logic_vector(15 downto 0);
......@@ -86,9 +81,20 @@ architecture rtl of vme_sfpga_bridge is
signal afpga_clk_n : std_logic;
type t_rx_state is (IDLE, RX_ADDR0, RX_ADDR1, RX_DATA0, RX_DATA1, RX_DATA2, RX_DATA3);
signal rx_state : t_rx_state;
type t_state is
(
IDLE, TX_CSR_REQ,
RX_CSR_ACK );
type t_rx_state is
(
IDLE,
RX_CONF0
);
signal state : t_state;
signal rx_state : t_state;
begin
afpga_clk_n <= not afpga_clk_i;
......@@ -149,69 +155,87 @@ begin
R => '0',
S => '0');
p_in_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
rx_state <= IDLE;
addr_req_o <= '0';
aux_valid_o <= '0';
else
case rx_state is
when IDLE =>
addr_req_o <= '0';
write_req_o <= '0';
if afpga_frame_in = '1' then
case afpga_din(15 downto 8) is
when c_tag_addr =>
report "[vmebridge] got addr tag";
rx_state <= RX_ADDR0;
addr_am_o <= afpga_din(7 downto 2);
addr_lword_n_o <= afpga_din(0);
when c_tag_aux =>
aux_valid_o <= '1';
aux_ga_o <= afpga_din(5 downto 0);
aux_iack_n_o <= afpga_din(6);
aux_iackin_n_o <= afpga_din(7);
rx_state <= IDLE;
when c_tag_write =>
write_ds_n_o <= afpga_din(1 downto 0);
rx_state <= RX_DATA0;
case afpga_din(15 downto 12) is
when c_tag_config =>
module_enable_o <= afpga_din(11);
bar_o <= afpga_din(10 downto 6);
rx_state <= RX_CONF0;
when others => null;
end case;
end if;
when RX_CONF0 =>
int_level_o <= afpga_din(2 downto 0);
int_vector_o <=afpga_din(15 downto 8);
irq_pending_o <= afpga_din(3);
rx_state <= IDLE;
end case;
end if;
end if;
end process;
p_out_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
state <= IDLE;
afpga_frame_out <= '0';
else
case state is
when IDLE =>
cr_csr_done_o <= '0';
afpga_frame_out <= '0';
if cr_csr_req_i = '1' then
afpga_frame_out <= '1';
afpga_dout <= c_tag_csr_req & cr_csr_we_i & cr_csr_addr_i(18 downto 5);
state <= TX_CSR_REQ;
end if;
if decode_start_i = '1' then
afpga_frame_out <= '1';
afpga_dout <= c_tag_decode_req & am_i & "000000";
state <= TX_DECODE_REQ0;
end if;
when TX_CSR_REQ =>
afpga_frame_out <= '0';
afpga_dout <= cr_csr_addr_i(4 downto 0) & "000" & cr_csr_data_i;
state <= RX_CSR_ACK;
when RX_CSR_ACK =>
if afpga_frame_in = '1' and afpga_din(15 downto 12) = c_tag_csr_rsp then
cr_csr_done_o <= '1';
cr_csr_data_o <= afpga_din(7 downto 0);
state <= IDLE;
end if;
when RX_ADDR0 =>
addr_o (31 downto 16) <= afpga_din;
rx_state <= RX_ADDR1;
when RX_ADDR1 =>
addr_o (15 downto 1) <= afpga_din(15 downto 1);
addr_req_o <= '1';
rx_state <= IDLE;
when TX_DECODE_REQ0 =>
afpga_dout <= addr_decoder_i(31 downto 16);
state <= TX_DECODE_REQ1;
when RX_DATA0 =>
write_data_o (63 downto 48) <= afpga_din;
rx_state <= RX_DATA1;
when RX_DATA1 =>
write_data_o (47 downto 32) <= afpga_din;
rx_state <= RX_DATA2;
when RX_DATA2 =>
write_data_o (31 downto 16) <= afpga_din;
rx_state <= RX_DATA3;
when RX_DATA3 =>
write_data_o (15 downto 0) <= afpga_din;
rx_state <= IDLE;
write_req_o <= '1';
when TX_DECODE_REQ1 =>
afpga_dout <= addr_decoder_i(15 downto 1) & '0';
state <= TX_DECODE_REQ1;
when RX_DECODE_RSP =>
......
hdl/rtl/xvme64x_core.vhd
View file @ 6f359655
......@@ -668,5 +668,4 @@ begin
user_csr_data_o <= s_user_csr_data_o;
user_csr_we_o <= s_user_csr_we;
assert wb_i.rty /= '1' report "rty not supported";
end rtl;
hdl/rtl/xvme64x_core_master.vhd 0 → 100644
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hdl/rtl/xvme64x_core_slave.vhd 0 → 100644
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