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VME64x core
Commits
32b8b233
Commit
32b8b233
authored
Dec 11, 2019
by
Tomasz Wlostowski
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get the thing to P&R successfully on a Kintex7
parent
143da27e
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6 changed files
with
649 additions
and
11 deletions
+649
-11
Manifest.py
hdl/rtl/Manifest.py
+2
-0
bridge_serdes_spartan6.vhd
hdl/rtl/platform/bridge_serdes_spartan6.vhd
+579
-0
serial_bridge_master.vhd
hdl/rtl/serial_bridge_master.vhd
+23
-3
serial_bridge_slave.vhd
hdl/rtl/serial_bridge_slave.vhd
+28
-4
xvme64x_core_master.vhd
hdl/rtl/xvme64x_core_master.vhd
+7
-2
xvme64x_core_slave.vhd
hdl/rtl/xvme64x_core_slave.vhd
+10
-2
No files found.
hdl/rtl/Manifest.py
View file @
32b8b233
...
...
@@ -8,6 +8,8 @@ files = ["serial_bridge_master.vhd",
"vme_funct_match.vhd"
,
"vme_irq_controller.vhd"
,
"vme_user_csr.vhd"
,
"platform/bridge_serdes_spartan6.vhd"
,
"platform/bridge_serdes_kintex7.vhd"
,
"xvme64x_bridge_serdes.vhd"
,
"xvme64x_core_master.vhd"
,
"xvme64x_core_slave.vhd"
,
...
...
hdl/rtl/
xvme64x_bridge_serdes
.vhd
→
hdl/rtl/
platform/bridge_serdes_spartan6
.vhd
View file @
32b8b233
This diff is collapsed.
Click to expand it.
hdl/rtl/serial_bridge_master.vhd
View file @
32b8b233
...
...
@@ -60,7 +60,10 @@ entity serial_bridge_master is
int_level_o
:
out
std_logic_vector
(
2
downto
0
);
int_vector_o
:
out
std_logic_vector
(
7
downto
0
);
irq_pending_o
:
out
std_logic
;
irq_ack_i
:
in
std_logic
irq_ack_i
:
in
std_logic
;
heartbeat_tx_o
:
out
std_logic
;
heartbeat_rx_o
:
out
std_logic
);
end
serial_bridge_master
;
...
...
@@ -118,11 +121,26 @@ architecture rtl of serial_bridge_master is
signal
tx_state
:
t_tx_state
;
signal
rx_state
:
t_rx_state
;
signal
heartbeat_cnt
:
unsigned
(
23
downto
0
);
signal
heartbeat
:
std_logic
;
begin
mem_ack_o
<=
mem_ack_int
;
heartbeat_tx_o
<=
heartbeat
;
process
(
afpga_clk_i
)
begin
if
rising_edge
(
afpga_clk_i
)
then
if
afpga_rst_n_i
=
'0'
then
heartbeat_cnt
<=
(
others
=>
'0'
);
else
heartbeat_cnt
<=
heartbeat_cnt
+
1
;
heartbeat
<=
std_logic
(
heartbeat_cnt
(
heartbeat_cnt
'length
-
1
)
);
end
if
;
end
if
;
end
process
;
afpga_d_o
<=
afpga_dout
;
afpga_frame_o
<=
afpga_frame_out
;
...
...
@@ -142,6 +160,7 @@ begin
when
c_tag_config0
=>
module_enable_o
<=
afpga_din
(
11
);
bar_o
<=
afpga_din
(
10
downto
6
);
heartbeat_rx_o
<=
afpga_din
(
5
);
when
c_tag_config1
=>
int_level_o
<=
afpga_din
(
2
downto
0
);
int_vector_o
<=
afpga_din
(
15
downto
8
);
...
...
@@ -207,7 +226,8 @@ begin
afpga_dout
(
15
downto
12
)
<=
c_tag_config0
;
afpga_dout
(
11
)
<=
vme_berr_n_i
;
afpga_dout
(
10
downto
6
)
<=
vme_ga_i
;
afpga_dout
(
5
downto
0
)
<=
(
others
=>
'0'
);
afpga_dout
(
5
)
<=
heartbeat
;
afpga_dout
(
4
downto
0
)
<=
(
others
=>
'0'
);
end
if
;
...
...
hdl/rtl/serial_bridge_slave.vhd
View file @
32b8b233
...
...
@@ -91,7 +91,11 @@ entity serial_bridge_slave is
int_level_i
:
in
std_logic_vector
(
2
downto
0
);
int_vector_i
:
in
std_logic_vector
(
7
downto
0
);
irq_pending_i
:
in
std_logic
;
irq_ack_o
:
out
std_logic
irq_ack_o
:
out
std_logic
;
heartbeat_tx_o
:
out
std_logic
;
heartbeat_rx_o
:
out
std_logic
);
end
serial_bridge_slave
;
...
...
@@ -147,17 +151,36 @@ architecture rtl of serial_bridge_slave is
signal
conf_cnt
:
unsigned
(
1
downto
0
);
signal
mem_data_reg
:
std_logic_vector
(
31
downto
0
);
signal
heartbeat_cnt
:
unsigned
(
23
downto
0
);
signal
heartbeat
:
std_logic
;
begin
heartbeat_tx_o
<=
heartbeat
;
process
(
sfpga_clk_i
)
begin
if
rising_edge
(
sfpga_clk_i
)
then
if
sfpga_rst_n_i
=
'0'
then
heartbeat_cnt
<=
(
others
=>
'0'
);
else
heartbeat_cnt
<=
heartbeat_cnt
+
1
;
heartbeat
<=
std_logic
(
heartbeat_cnt
(
heartbeat_cnt
'length
-
1
)
);
end
if
;
end
if
;
end
process
;
sfpga_frame_in
<=
sfpga_frame_i
;
sfpga_din
<=
sfpga_d_i
;
sfpga_frame_o
<=
sfpga_frame_out
;
sfpga_d_o
<=
sfpga_dout
;
p_in_fsm
:
process
(
sfpga_clk_i
)
p_in_fsm
:
process
(
sfpga_clk_i
)
variable
send_cfg
:
boolean
:
=
false
;
begin
if
rising_edge
(
sfpga_clk_i
)
then
...
...
@@ -202,6 +225,7 @@ begin
-- report "decode conf0 req";
vme_berr_n_o
<=
sfpga_din
(
11
);
vme_ga_o
<=
sfpga_din
(
10
downto
6
);
heartbeat_rx_o
<=
sfpga_din
(
5
);
vme_aux_valid_o
<=
'1'
;
send_cfg
:
=
true
;
elsif
sfpga_din
(
15
downto
12
)
=
c_tag_csr_req
then
...
...
@@ -238,7 +262,7 @@ begin
sfpga_dout
(
15
downto
12
)
<=
c_tag_config0
;
sfpga_dout
(
11
)
<=
module_enable_i
;
sfpga_dout
(
10
downto
6
)
<=
bar_i
;
sfpga_dout
(
5
)
<=
heartbeat
;
elsif
conf_cnt
=
1
then
sfpga_frame_out
<=
'1'
;
...
...
hdl/rtl/xvme64x_core_master.vhd
View file @
32b8b233
...
...
@@ -56,7 +56,10 @@ entity xvme64x_core_master is
afpga_d_i
:
in
std_logic_vector
(
15
downto
0
);
afpga_frame_i
:
in
std_logic
;
afpga_d_o
:
out
std_logic_vector
(
15
downto
0
);
afpga_frame_o
:
out
std_logic
afpga_frame_o
:
out
std_logic
;
heartbeat_rx_o
:
out
std_logic
;
heartbeat_tx_o
:
out
std_logic
);
end
xvme64x_core_master
;
...
...
@@ -303,7 +306,9 @@ begin
int_level_o
=>
s_irq_level
,
int_vector_o
=>
s_irq_vector
,
irq_pending_o
=>
s_irq_pending
,
irq_ack_i
=>
s_irq_ack
);
irq_ack_i
=>
s_irq_ack
,
heartbeat_rx_o
=>
heartbeat_rx_o
,
heartbeat_tx_o
=>
heartbeat_tx_o
);
end
rtl
;
hdl/rtl/xvme64x_core_slave.vhd
View file @
32b8b233
...
...
@@ -138,7 +138,13 @@ entity xvme64x_core_slave is
-- User CR
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
));
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
heartbeat_tx_o
:
out
std_logic
;
heartbeat_rx_o
:
out
std_logic
);
end
xvme64x_core_slave
;
architecture
rtl
of
xvme64x_core_slave
is
...
...
@@ -313,7 +319,9 @@ begin
int_level_i
=>
s_irq_level
,
int_vector_i
=>
s_irq_vector
,
irq_pending_i
=>
s_irq_pending
,
irq_ack_o
=>
s_irq_ack
);
irq_ack_o
=>
s_irq_ack
,
heartbeat_rx_o
=>
heartbeat_rx_o
,
heartbeat_tx_o
=>
heartbeat_tx_o
);
inst_vme_funct_match
:
entity
work
.
vme_funct_match
...
...
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