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VME64x core
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VME64x core
Commits
42f6c768
Commit
42f6c768
authored
Sep 13, 2022
by
Tomasz Wlostowski
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HDL: fixes in the verilog wrapper of the core
parent
e2962d50
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3 changed files
with
53 additions
and
0 deletions
+53
-0
Manifest.py
hdl/rtl/Manifest.py
+1
-0
vme64x_core_verilog.vhd
hdl/rtl/vme64x_core_verilog.vhd
+14
-0
vme64x_bfm_pkg.sv
hdl/sim/vme64x_bfm/vme64x_bfm_pkg.sv
+38
-0
No files found.
hdl/rtl/Manifest.py
View file @
42f6c768
files
=
[
"vme64x_core.vhd"
,
files
=
[
"vme64x_core.vhd"
,
"vme64x_core_verilog.vhd"
,
"vme64x_pkg.vhd"
,
"vme64x_pkg.vhd"
,
"vme_bus.vhd"
,
"vme_bus.vhd"
,
"vme_cr_csr_space.vhd"
,
"vme_cr_csr_space.vhd"
,
...
...
hdl/rtl/vme64x_core_verilog.vhd
View file @
42f6c768
...
@@ -23,6 +23,7 @@ entity vme64x_core_verilog is
...
@@ -23,6 +23,7 @@ entity vme64x_core_verilog is
g_VME32
:
natural
:
=
1
;
g_VME32
:
natural
:
=
1
;
g_VME_2e
:
natural
:
=
0
;
g_VME_2e
:
natural
:
=
0
;
g_WB_GRANULARITY
:
string
(
1
to
4
);
g_WB_GRANULARITY
:
string
(
1
to
4
);
g_WB_MODE
:
string
;
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
);
g_MANUFACTURER_ID
:
std_logic_vector
(
23
downto
0
);
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
);
g_BOARD_ID
:
std_logic_vector
(
31
downto
0
);
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
);
g_REVISION_ID
:
std_logic_vector
(
31
downto
0
);
...
@@ -131,8 +132,20 @@ entity vme64x_core_verilog is
...
@@ -131,8 +132,20 @@ entity vme64x_core_verilog is
return
BYTE
;
return
BYTE
;
end
if
;
end
if
;
end
string_to_wb_grn
;
end
string_to_wb_grn
;
function
string_to_wb_mode
(
X
:
string
)
return
t_wishbone_interface_mode
is
begin
if
X
=
"CLASSIC"
then
return
CLASSIC
;
end
if
;
if
X
=
"PIPELINED"
then
return
PIPELINED
;
end
if
;
end
string_to_wb_mode
;
end
vme64x_core_verilog
;
end
vme64x_core_verilog
;
architecture
wrapper
of
vme64x_core_verilog
is
architecture
wrapper
of
vme64x_core_verilog
is
begin
begin
inst
:
entity
work
.
vme64x_core
inst
:
entity
work
.
vme64x_core
...
@@ -144,6 +157,7 @@ begin
...
@@ -144,6 +157,7 @@ begin
g_VME32
=>
nat_to_bool
(
g_VME32
),
g_VME32
=>
nat_to_bool
(
g_VME32
),
g_VME_2e
=>
nat_to_bool
(
g_VME_2e
),
g_VME_2e
=>
nat_to_bool
(
g_VME_2e
),
g_WB_GRANULARITY
=>
string_to_wb_grn
(
g_WB_GRANULARITY
),
g_WB_GRANULARITY
=>
string_to_wb_grn
(
g_WB_GRANULARITY
),
g_WB_MODE
=>
string_to_wb_mode
(
g_WB_MODE
),
g_MANUFACTURER_ID
=>
g_MANUFACTURER_ID
,
g_MANUFACTURER_ID
=>
g_MANUFACTURER_ID
,
g_BOARD_ID
=>
g_BOARD_ID
,
g_BOARD_ID
=>
g_BOARD_ID
,
g_REVISION_ID
=>
g_REVISION_ID
,
g_REVISION_ID
=>
g_REVISION_ID
,
...
...
hdl/sim/vme64x_bfm/vme64x_bfm_pkg.sv
View file @
42f6c768
...
@@ -507,4 +507,42 @@ class CBusAccessor_VME64x extends CBusAccessor;
...
@@ -507,4 +507,42 @@ class CBusAccessor_VME64x extends CBusAccessor;
endtask
// handle_irqs
endtask
// handle_irqs
endclass
// CBusAccessor_VME64x
endclass
// CBusAccessor_VME64x
class
CVME16to32Accessor
extends
CBusAccessor
;
protected
CBusAccessor_VME64x
m_acc
;
function
new
(
CBusAccessor_VME64x
acc_
)
;
m_acc
=
acc_
;
endfunction
// new
virtual
task
automatic
writem
(
input
u64_vector_t
addr
,
u64_vector_t
data
,
input
int
size
,
ref
int
result
)
;
endtask
// writem
virtual
task
automatic
readm
(
input
u64_vector_t
addr
,
ref
u64_vector_t
data
,
input
int
size
,
ref
int
result
)
;
endtask
// readm
virtual
task
automatic
read
(
uint64_t
addr
,
ref
uint64_t
data
,
input
int
size
=
4
,
ref
int
result
=
_
null
)
;
uint64_t
rv
;
m_acc
.
read
(
addr
,
rv
,
D16Byte01
|
A24
|
SINGLE
)
;
data
=
(
rv
<<
16
)
;
m_acc
.
read
(
addr
+
2
,
rv
,
D16Byte23
|
A24
|
SINGLE
)
;
data
|=
(
rv
&
'hffff
)
;
endtask
virtual
task
automatic
write
(
uint64_t
addr
,
uint64_t
data
,
int
size
=
4
,
ref
int
result
=
_
null
)
;
// $display("Write32to16 %x %x", addr, data);
m_acc
.
write
(
addr
,
(
data
>>
16
)
,
D16Byte01
|
A24
|
SINGLE
)
;
m_acc
.
write
(
addr
+
2
,
(
data
&
'hffff
)
,
D16Byte23
|
A24
|
SINGLE
)
;
endtask
endclass
// CWishboneAccessor
endpackage
endpackage
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