Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
V
VME64x core
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
VME64x core
Commits
48db76c6
Commit
48db76c6
authored
Sep 06, 2021
by
Tomasz Wlostowski
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
rtl: connect and safely drive remaining memory I/F signals
parent
87a162be
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
3 additions
and
0 deletions
+3
-0
serial_bridge_slave.vhd
hdl/rtl/serial_bridge_slave.vhd
+2
-0
xvme64x_core_master.vhd
hdl/rtl/xvme64x_core_master.vhd
+1
-0
No files found.
hdl/rtl/serial_bridge_slave.vhd
View file @
48db76c6
...
...
@@ -195,6 +195,8 @@ begin
sfpga_dout
<=
(
others
=>
'0'
);
sfpga_frame_out
<=
'0'
;
mem_we_o
<=
'0'
;
else
...
...
hdl/rtl/xvme64x_core_master.vhd
View file @
48db76c6
...
...
@@ -225,6 +225,7 @@ begin
mem_addr_o
=>
mem_addr
,
mem_is_blt_o
=>
mem_is_blt
,
mem_we_o
=>
mem_we
,
mem_sel_o
=>
mem_sel
,
-- Function decoder
addr_decoder_i
=>
s_addr_decoder_o
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment