hdl: commented out unused code

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

hdl: commented out unused code
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>
4acf0b36 · Jan Pospisil · Dimitris Lampridis · 38400808 · 4acf0b36 · 4acf0b36
Commit 4acf0b36 authored Aug 24, 2016 by Jan Pospisil Committed by Dimitris Lampridis Dec 13, 2016
Showing with 18 additions and 14 deletions

VME64xCore_Top.vhd hdl/vme64x-core/rtl/VME64xCore_Top.vhd +3 -3

VME_CR_CSR_Space.vhd hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd +4 -4

VME_bus.vhd hdl/vme64x-core/rtl/VME_bus.vhd +11 -7

No files found.
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -220,8 +220,8 @@ architecture RTL of VME64xCore_Top is
  signal s_FIFOreset           : std_logic;
  signal s_VME_DATA_IRQ        : std_logic_vector(31 downto 0);
  signal s_VME_DATA_VMEbus     : std_logic_vector(31 downto 0);
-  signal s_VME_DATA_b          : std_logic_vector(31 downto 0);
+  -- signal s_VME_DATA_b          : std_logic_vector(31 downto 0);
-  signal s_fifo                : std_logic;
+  -- signal s_fifo                : std_logic;
  signal s_VME_DTACK_VMEbus    : std_logic;
  signal s_VME_DTACK_IRQ       : std_logic;
  signal s_VME_DTACK_OE_VMEbus : std_logic;
@@ -256,7 +256,7 @@ architecture RTL of VME64xCore_Top is
  -- Oversampled input signals 
  signal VME_RST_n_oversampled    : std_logic;
  signal VME_AS_n_oversampled     : std_logic;
-  signal VME_AS_n_oversampled1    : std_logic;  -- for the IRQ_Controller
+  --signal VME_AS_n_oversampled1    : std_logic;  -- for the IRQ_Controller
  --signal VME_LWORD_n_oversampled   : std_logic;
  signal VME_WRITE_n_oversampled  : std_logic;
  signal VME_DS_n_oversampled     : std_logic_vector(1 downto 0);

--- a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
@@ -175,13 +175,13 @@ architecture Behavioral of VME_CR_CSR_Space is
   signal s_bar_written          : std_logic;
   signal s_CSRdata              : unsigned(7 downto 0);
   signal s_FUNC_ADER            : t_FUNC_32b_array;
-	signal s_CR_Space             : t_cr_array(2**12 downto 0);
+   signal s_CR_Space             : t_cr_array(2**12 downto 0);
   signal s_CrCsrOffsetAddr      : unsigned(18 downto 0);
   signal s_locDataIn            : unsigned(7 downto 0);
   signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
   signal s_odd_parity           : std_logic;
-	signal s_BARerror             : std_logic;
+   --signal s_BARerror             : std_logic;
-	signal s_BAR_o                : std_logic_vector(4 downto 0);
+   signal s_BAR_o                : std_logic_vector(4 downto 0);
 --===========================================================================
 -- Architecture begin
 --===========================================================================
@@ -193,7 +193,7 @@ s_odd_parity   <=  VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
 -- If the crate is not driving the GA lines or the parity is even the BAR register
 -- is set to 0x00 and the following flag is asserted; the board will not answer if the 
 -- master accesses its  CR/CSR space and we can see a time out error in the VME bus.  
-s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));		
+--s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
 --------------------------------------------------------------------------------
 s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
 -- CR

--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -183,11 +183,12 @@ architecture RTL of VME_bus is
  signal s_locAddrBeforeOffset    : unsigned(63 downto 0);
  signal s_phase1addr             : unsigned(63 downto 0);  -- for 2e transfers
  signal s_phase2addr             : unsigned(63 downto 0);  --
-  signal s_phase3addr             : unsigned(63 downto 0);  --
+  -- signal s_phase3addr             : unsigned(63 downto 0);  --
  signal s_addrOffset             : unsigned(17 downto 0);  -- block transfers|
  signal s_CrCsrOffsetAddr        : unsigned(18 downto 0);  -- CR/CSR address 
  signal s_DataShift              : unsigned(5 downto 0);
-  signal s_2eLatchAddr            : std_logic_vector(1 downto 0);  -- for 2e transfers
+  -- uncomment if 2e is implemented:
+  --signal s_2eLatchAddr            : std_logic_vector(1 downto 0);  -- for 2e transfers
  signal s_locDataSwap            : std_logic_vector(63 downto 0);
  signal s_locDataInSwap          : std_logic_vector(63 downto 0);
  signal s_locDataOutWb           : std_logic_vector(63 downto 0);
@@ -230,9 +231,10 @@ architecture RTL of VME_bus is
  signal s_transferActive     : std_logic;  -- active VME transfer
 --   signal s_retry                     : std_logic;  -- RETRY signal
  signal s_retry_out          : std_logic;
-  signal s_berr               : std_logic;  -- BERR signal
+  -- uncomment if 2e is implemented:
-  signal s_berr_1             : std_logic;  --                            
+  --signal s_berr               : std_logic;  -- BERR signal
-  signal s_berr_2             : std_logic;  --    
+  -- signal s_berr_1             : std_logic;  --               -- uncomment if 2e is implemented:
+  -- signal s_berr_2             : std_logic;  --               -- uncomment if 2e is implemented:
  -- Access decode signals
  signal s_confAccess : std_logic;      -- Asserted when CR or CSR is addressed
@@ -442,9 +444,11 @@ begin
  s_dataToOutput   <= s_FSM.s_dataToOutput;
  s_dataToAddrBus  <= s_FSM.s_dataToAddrBus;
  s_transferActive <= s_FSM.s_transferActive;
-  s_2eLatchAddr    <= s_FSM.s_2eLatchAddr;
+  -- uncomment if 2e is implemented:
+  --s_2eLatchAddr    <= s_FSM.s_2eLatchAddr;
  s_retry_out      <= s_FSM.s_retry;
-  s_berr           <= s_FSM.s_berr;
+  -- uncomment if 2e is implemented:
+  --s_berr           <= s_FSM.s_berr;
  s_BERR_out       <= s_FSM.s_BERR_out;
  p_VMEmainFSM : process(clk_i)