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VME64x core
Commit 4e43e935 authored by dpedrett's avatar dpedrett
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VFC testbench uploaded 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@174 665b4545-5c6b-4c24-801b-41150b02b44b
parent e01aa109
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hdl/boards/vfc/SFpga.ucf
View file @ 4e43e935
...@@ -241,7 +241,7 @@ NET "clk_i" LOC = B14; ...@@ -241,7 +241,7 @@ NET "clk_i" LOC = B14;
NET "clk_i" TNM_NET = "clk_i_group"; NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%; #TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30 #Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%; TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 40 ns HIGH 50%;
# Add by Davide for debug # Add by Davide for debug
NET "leds[0]" LOC = P5; NET "leds[0]" LOC = P5;
NET "leds[1]" LOC = R4; NET "leds[1]" LOC = R4;
...@@ -252,5 +252,96 @@ NET "leds[5]" LOC = U3; ...@@ -252,5 +252,96 @@ NET "leds[5]" LOC = U3;
NET "leds[6]" LOC = U4; NET "leds[6]" LOC = U4;
NET "leds[7]" LOC = T4; NET "leds[7]" LOC = T4;
#logic level:
NET "VME_GA_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[2]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[3]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[4]" IOSTANDARD = LVCMOS33;
NET "VME_GA_i[5]" IOSTANDARD = LVCMOS33;
NET "VME_DS_n_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_DS_n_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_DTACK_n_o" IOSTANDARD = LVCMOS33;
NET "VME_LWORD_n_b" IOSTANDARD = LVCMOS33;
NET "VME_IACKIN_n_i" IOSTANDARD = LVCMOS33;
NET "VME_IACKOUT_n_o" IOSTANDARD = LVCMOS33;
NET "VME_IACK_n_i" IOSTANDARD = LVCMOS33;
NET "VME_WRITE_n_i" IOSTANDARD = LVCMOS33;
NET "VME_AS_n_i" IOSTANDARD = LVCMOS33;
NET "VME_BERR_o" IOSTANDARD = LVCMOS33;
NET "VME_RETRY_n_o" IOSTANDARD = LVCMOS33;
NET "VME_RETRY_OE_o" IOSTANDARD = LVCMOS33;
NET "VME_RST_n_i" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_DIR_o" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_OE_N_o" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[0]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[1]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[2]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[3]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[4]" IOSTANDARD = LVCMOS33;
NET "VME_AM_i[5]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[1]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[2]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[3]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[4]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[5]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[6]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[7]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[8]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[9]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[10]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[11]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[12]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[13]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[14]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[15]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[16]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[17]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[18]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[19]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[20]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[21]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[22]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[23]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[24]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[25]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[26]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[27]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[28]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[29]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[30]" IOSTANDARD = LVCMOS33;
NET "VME_ADDR_b[31]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[0]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[1]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[2]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[3]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[4]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[5]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[6]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[7]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[8]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[9]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[10]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[11]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[12]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[13]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[14]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[15]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[16]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[17]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[18]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[19]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[20]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[21]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[22]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[23]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[24]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[25]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[26]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[27]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[28]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[29]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[30]" IOSTANDARD = LVCMOS33;
NET "VME_DATA_b[31]" IOSTANDARD = LVCMOS33;
hdl/boards/vfc/sim/testbench/VME64x_Package.vhd
View file @ 4e43e935
...@@ -74,7 +74,7 @@ type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LC ...@@ -74,7 +74,7 @@ type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LC
-- constant <constant_name> : time := <time_unit> ns; -- constant <constant_name> : time := <time_unit> ns;
constant BA : std_logic_vector(7 downto 0) := "11110000"; constant BA : std_logic_vector(7 downto 0) := "11110000";
constant VME_GA : std_logic_vector(5 downto 0) := "010111"; -- GA parity match '1' & slot number constant VME_GA : std_logic_vector(5 downto 0) := "110111"; -- GA parity match '1' & slot number
constant ID_Master : std_logic_vector(7 downto 0) := "00001111"; -- max 31 constant ID_Master : std_logic_vector(7 downto 0) := "00001111"; -- max 31
constant ADER0_A16_S : std_logic_vector(31 downto 0) := "0000000000000000" & BA(7 downto 3) & "000" & c_A16 &"00"; constant ADER0_A16_S : std_logic_vector(31 downto 0) := "0000000000000000" & BA(7 downto 3) & "000" & c_A16 &"00";
constant ADER0_A24_S : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_S &"00"; constant ADER0_A24_S : std_logic_vector(31 downto 0) := "00000000" & BA(7 downto 3) & "00000000000" & c_A24_S &"00";
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ 4e43e935
This diff is collapsed.
hdl/boards/vfc/syn/VME64xTest.xise
View file @ 4e43e935
...@@ -16,51 +16,51 @@ ...@@ -16,51 +16,51 @@
<files> <files>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file> </file>
<file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../rtl/ram_8bits.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/ram_8bits.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../rtl/spram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="../sim/testbench/VME64x_TB.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../sim/testbench/VME64x_TB.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="62"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="62"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="62"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="62"/>
</file> </file>
<file xil_pn:name="../sim/testbench/VME64x_SIM_Package.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../sim/testbench/VME64x_SIM_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="63"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="63"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="63"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="63"/>
</file> </file>
<file xil_pn:name="../sim/testbench/VME64x_Package.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../sim/testbench/VME64x_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="64"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="64"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="64"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="64"/>
...@@ -73,56 +73,64 @@ ...@@ -73,56 +73,64 @@
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_DpBlockRam.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../rtl/genram_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="../rtl/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../rtl/xwb_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/xwb_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../rtl/IRQ_Generator_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../rtl/WB_Bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CRAM.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
</files> </files>
......
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