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VME64x core
Commit 5b96f5a4 authored by dpedrett's avatar dpedrett
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Fixed the timing problem. Now the BLT and MBLT accesses are working fine. Program ID = 0x58. 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@163 665b4545-5c6b-4c24-801b-41150b02b44b
parent 5e23c326
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Showing with 167 additions and 197 deletions
hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 5b96f5a4
......@@ -290,6 +290,17 @@ begin
reg_o => VME_DS_n_oversampled,
clk_i => clk_i
);
-- to avoid timing problem during BLT and MBLT accesses
DSinputSample1 : DoubleRegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled_1,
clk_i => clk_i
);
WRITEinputSample : SigInputSample
port map(
......@@ -349,9 +360,9 @@ begin
Inst_VME_bus: VME_bus
generic map(
g_width => c_width,
g_addr_width => c_addr_width,
g_CRAM_SIZE => c_CRAM_SIZE
g_width => g_width,
g_addr_width => g_addr_width,
g_CRAM_SIZE => g_CRAM_SIZE
)
port map(
clk_i => clk_i,
......@@ -365,6 +376,7 @@ begin
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => VME_WRITE_n_oversampled,
VME_DS_n_i => VME_DS_n_oversampled,
VME_DS_ant_n_i => VME_DS_n_oversampled_1,
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
......@@ -474,7 +486,8 @@ begin
--CR/CSR space
Inst_VME_CR_CSR_Space: VME_CR_CSR_Space
generic map(
g_CRAM_SIZE => c_CRAM_SIZE
g_CRAM_SIZE => g_CRAM_SIZE,
g_width => g_width
)
port map(
clk_i => clk_i,
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 5b96f5a4
......@@ -123,7 +123,8 @@ use work.VME_CSR_pack.all;
--===========================================================================
entity VME_CR_CSR_Space is
generic(
g_CRAM_SIZE : integer := c_CRAM_SIZE
g_CRAM_SIZE : integer := c_CRAM_SIZE;
g_width : integer := c_width
);
Port ( -- VMEbus.vhd signals
clk_i : in std_logic;
......@@ -276,7 +277,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
end case;
else
if c_width = 32 then
if g_width = 32 then
s_CSRarray(WB32bits) <= x"01";
else
s_CSRarray(WB32bits) <= x"00";
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 5b96f5a4
......@@ -149,7 +149,7 @@ package VME_CR_pack is
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"55",
16#1F# => x"58",
--Offset to BEG_USER_CR
16#20# => x"00",
16#21# => x"00",
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 5b96f5a4
......@@ -153,38 +153,31 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 3,c_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 3,g_addr_width));
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if sel = "10000000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 56);
elsif sel = "01000000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
elsif sel = "00100000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 40);
elsif sel = "00010000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
elsif sel = "00001000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 24);
elsif sel = "00000100" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
elsif sel = "00000010" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 8);
elsif sel = "11000000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
elsif sel = "00110000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
elsif sel = "00001100" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
elsif sel = "11110000" then
WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
else
WBdata_o <= locDataInSwap;
end if;
case sel is
when "10000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 56);
when "01000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
when "00100000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 40);
when "00010000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 24);
when "00000100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
when "00000010" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 8);
when "11000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
when "00110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
when "11110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001111" => WBdata_o <= locDataInSwap;
when "00000001" => WBdata_o <= locDataInSwap;
when "00000011" => WBdata_o <= locDataInSwap;
when "11111111" => WBdata_o <= locDataInSwap;
when others => null;
end case;
WbSel_o <= std_logic_vector(sel);
end if;
end process;
......@@ -235,7 +228,7 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 2,c_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 2,g_addr_width));
end if;
end process;
......@@ -252,28 +245,27 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
if sel = "10000000" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,c_width));
elsif sel = "01000000" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,c_width));
elsif sel = "00100000" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,c_width));
elsif sel = "00001000" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,c_width));
elsif sel = "00000100" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,c_width));
elsif sel = "00000010" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,c_width));
elsif sel = "11000000" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,c_width));
elsif sel = "00001100" then
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,c_width));
else
WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),c_width));
end if;
case sel is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,g_width));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,g_width));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,g_width));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,g_width));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when others => null;
end case;
if s_shift_dx = '1' then
WbSel_o <= sel(7 downto 4); -- b"0000" &
WbSel_o <= sel(7 downto 4);
else
WbSel_o <= sel(3 downto 0);
end if;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 5b96f5a4
This diff is collapsed.
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 5b96f5a4
......@@ -61,12 +61,12 @@ package vme64x_pack is
--_______________________________________________________________________________
-- Constants:
--WB data width:
constant c_width : integer := 32; --must be 32 or 64!
constant c_width : integer := 64; --must be 32 or 64!
--CRAM size in the CR/CSR space (bytes):
constant c_CRAM_SIZE : integer := 1024;
-- remember to set properly the "END_CRAM" register in the CR space
-- WB addr width:
constant c_addr_width : integer := 10;
constant c_addr_width : integer := 9;
--
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
......@@ -374,6 +374,7 @@ function f_log2_size (A : natural) return natural;
VME_LWORD_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_DS_ant_n_i : in std_logic_vector(1 downto 0);
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
......@@ -524,7 +525,8 @@ function f_log2_size (A : natural) return natural;
component VME_CR_CSR_Space is
generic(
g_CRAM_SIZE : integer := c_CRAM_SIZE
g_CRAM_SIZE : integer := c_CRAM_SIZE;
g_width : integer := c_width
);
port(
clk_i : in std_logic;
......
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